SLVSFR3B april   2022  – june 2023 TPSI2140-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Avalanche Robustness
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Dielectric Withstand Testing (HiPot)
      2. 9.2.2 Design Requirements
      3. 9.2.3 Design Procedure - Chassis Ground Reference
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Qualified for automotive applications
    • AEC-Q100 grade 1: –40 to 125°C TA
  • Integrated avalanche rated MOSFETs
    • Designed and qualified for reliability during overvoltage conditions, including system level dielectric withstand testing (Hi-Pot)
      • IAVA = 2-mA for 5-s pulses, 1-mA for 60-s pulses
    • 1200-V standoff voltage
    • RON = 130-Ω (TJ = 25°C)
    • TON, TOFF < 700-μs
  • Low primary side supply current
    • 9-mA ON state current
    • 3.5-μA OFF state current
  • Functional Safety Capable
  • Robust isolation barrier:
    • > 26 year projected lifetime at 1000-VRMS / 1500-VDC working voltage
    • Isolation rating, VISO, up to 3750-VRMS / 5300-VDC
    • Peak surge, VIOSM, up to 5000-V
    • ± 100-V/ns typical CMTI
  • SOIC 11-pin (DWQ) package with wide pins for improved thermal performance
    • Creepage and clearance ≥ 8-mm (primary-secondary)
    • Creepage and clearance ≥ 6-mm (across switch terminals)
  • Safety-related certifications
    • (Planned) DIN VDE V 0884-11:2017-01
    • (Planned) UL 1577 component recognition program