SLVSG43B December   2023  – July 2025 TPSI3100-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristic Curves
    12. 6.12 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Transmission of the Enable State
      2. 8.3.2 Power Transmission
      3. 8.3.3 Gate Driver
      4. 8.3.4 Chip Enable (CE)
      5. 8.3.5 Comparators
        1. 8.3.5.1 Fault Comparator
        2. 8.3.5.2 Alarm Comparator
        3. 8.3.5.3 Comparator De-glitch
      6. 8.3.6 VDDP, VDDH, and VDDM Undervoltage Lockout (UVLO)
      7. 8.3.7 Keep-Off Circuitry
      8. 8.3.8 Thermal Shutdown
    4. 8.4 Device Operation
    5. 8.5 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 CDIV1, CDIV2 Capacitance
        2. 9.2.2.2 Start-up Time and Recovery Time
        3. 9.2.2.3 RSHUNT, R1, and R2 Selection
        4. 9.2.2.4 Overcurrent Fault Error
        5. 9.2.2.5 Overcurrent Alarm Error
        6. 9.2.2.6 VDDP Capacitance, CVDDP
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DVX|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.5 Device Functional Modes

Table 8-1 summarizes the functional modes for the TPSI310x-Q1 and TPSI310xL-Q1.

Table 8-1 TPSI310x-Q1, TPSI311x-Q1, TPSI312x-Q1, and TPSI3133-Q1 family, Functional Modes(1)(2)
CE VDDP VDDH, VDDM EN VDRV PGOOD COMMENTS
X Powered Down(4) Powered Down(6) X L Hi-Z Powered Down:
VDRV output disabled, keep off circuitry applied.
L Powered Up(3) Powered Down(6) X L L Disabled Operation:
When CE is asserted low, power transfer to the secondary ceases. VDDH and VDDM rails discharge pending loading. VDRV output disabled, keep off circuitry applied.
H Powered Up(3) Powered Up(5) L L H Normal Operation: VDRV output state follows logic state of EN logic state.
H H H
X Powered Down(4) Powered Up(5) X L L Disabled Operation:
When VDDP is powered down, output driver is disabled automatically. If sufficient VDDP power is available, VDRV is disabled within the propagation delay, otherwise after the timeout duration. Keep off circuitry applied.
(1) No alarm or fault conditions present (FLTn_CMP = ALMn_CMP = 0).
(2) X: do-not-care.
(3) VVDDP ≥ VDDP_UVLO threshold.
(4) VVDDP < VDDP_UVLO threshold.
(5) VVDDH ≥ VDDH_UVLO threshold and VVDDM ≥ VDDM_UVLO threshold.
(6) VVDDH <VDDH_UVLO threshold or VVDDM < VDDM_UVLO threshold.

Table 8-2 summarizes fault and comparator functional behavior.

Table 8-2 FLTn, ALMn Functional Behavior(1)
CE(2) FLTn_CMP(3) ALMn_CMP(4) FLTn(5) ALMn(5) COMMENTS
L X X L L VDRV output disabled, keep off circuitry applied.
H L L Hi-Z Hi-Z VDRV output follows state of EN pin.
H L H Hi-Z L Fault detected. VDRV output asserted low until recovery timer elapses. On latched fault devices, VDRV asserts low and remains low until EN asserts low then high and recovery timer elapses.
H H L L Hi-Z Alarm detected. VDRV output unchanged.
H H H L L Fault and alarm detected. VDRV output asserted low until recovery timer elapses. On latched fault devices, VDRV asserts low and remains low until EN asserts low then high and recovery timer elapses.
(1) Assumes VVDDP ≥ VDDP_UVLO threshold and device is fully powered in steady state conditions.
(2) L: VCE < VIT_-(CE), H: VCE ≥ VIT_+(CE).
(3) L: VFLTn_CMP < VREF, H: VFLTn_CMP ≥ VREF.
(4) L: VALMn_CMP < VREF, H: VALMn_CMP ≥ VREF.
(5) Hi-Z: Open-drain output disabled, L: Open-drain output enabled.