SLVSDT1C July 2017 – June 2020 TPSM82480
A recommended PCB layout for the TPSM82480 dual phase solution is shown below. It ensures best electrical and optimized thermal performance considering the following important topics:
- Both VOUT1 and VOUT2 must be connected to build a common VOUT structure.
- The input capacitors must be placed as close as possible to the appropriate pins of the device. This provides low resistive and inductive paths for the high di/dt input current. The input capacitance is split, as is the VIN connection, to avoid interference between the input lines.
- The VOUT regulation loop is closed with COUT and its ground connection. To avoid PGND noise crosstalk, PGND is kept split for the regulation loop. If a ground layer or plane is used, a direct connection by vias, as shown, is recommended. Otherwise the connection of COUT to GND must be short for good load regulation.
- The FB node is sensitive to dv/dt signals. Therefore the resistive divider should be placed close to the FB (and RS pin in case of using R3) pin, avoiding long trace distance.
For more detailed information about the actual EVM solution, see the TPSM82480EVM-002 User's Guide.