SLLS825C August   2007  – December 2024 TRSF3232E

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  ESD Protection, Driver
    4. 5.4  ESD Protection, Receiver
    5. 5.5  Recommended Operating Conditions
    6. 5.6  Thermal Information
    7. 5.7  Electrical Characteristics
    8. 5.8  Electrical Characteristics, Driver
    9. 5.9  Electrical Characteristics, Receiver
    10. 5.10 Switching Characteristics, Driver
    11. 5.11 Switching Characteristics, Reveiver
    12. 5.12 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power
      2. 7.3.2 RS232 Driver
      3. 7.3.3 RS232 Receiver
    4. 7.4 Device Functional Modes
      1. 7.4.1 VCC Powered by 3V to 5.5V
      2. 7.4.2 VCC Unpowered, VCC = 0V
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Performance Plots
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.4 ESD Protection, Receiver

PIN NAMETEST CONDITIONSTYPUNIT
RIN1, RIN2(2)HBM±15kV
IEC 61000-4-2 Air-Gap Discharge (1)±15
IEC 61000-4-2 Contact Discharge (1)±8
(1) For RGT, D and PW packages only:A minimum of 1-µF capacitor is needed between VCC and GND to meet the specified IEC ESD level.
(2) For optimized IEC ESD performance for DYY package, the recommendation is to have series resistor (≥ 50Ω), on all logic inputs directly connected to power or ground, to minimize the transient currents going into or out of the logic pins.