SLLSFL2 April   2022 TUSB1142

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Revision History
  4. 4 Pin Configuration and Functions
  5. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Supply Characteristics
    6. 5.6  Control I/O DC Electrical Characteristics
    7. 5.7  USB Electrical Characteristics
    8. 5.8  Timing Requirements
    9. 5.9  Switching Characteristics
    10. 5.10 Typical Characteristics
  6. 6 Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 4-Level Inputs
      2. 7.3.2 USB Receiver Linear Equalization
        1. 7.3.2.1 Linear EQ Configuration
        2. 7.3.2.2 Full Adaptive Equalization
        3. 7.3.2.3 Fast Adaptive Equalization
      3. 7.3.3 USB Transmitter
        1. 7.3.3.1 Linearity VOD
        2. 7.3.3.2 Limited VOD
        3. 7.3.3.3 Transmit Equalization (Limited Redriver Mode Only)
      4. 7.3.4 USB 3.2 2:1 MUX Description
      5. 7.3.5 USB Polarity Inversion
      6. 7.3.6 Receiver Detect Control
    4. 7.4 Device Functional Modes
      1. 7.4.1 MODE Pin
      2. 7.4.2 Rx EQ Configuration in Pin-Strap Mode
      3. 7.4.3 USB 3.2 Power States
      4. 7.4.4 Disabling U1 and U2
    5. 7.5 Programming
      1. 7.5.1 Pseudocode Examples
        1. 7.5.1.1 Fixed EQ with Linear Redriver Mode
        2. 7.5.1.2 Fixed EQ with Limited Redriver Mode
        3. 7.5.1.3 Fast AEQ with Linear Redriver Mode
        4. 7.5.1.4 Fast AEQ with Limited Redriver Mode
        5. 7.5.1.5 Full AEQ with Linear Redriver Mode
        6. 7.5.1.6 Full AEQ with Limited Redriver Mode
      2. 7.5.2 TUSB1142 I2C Address Options
      3. 7.5.3 TUSB1142 I2C Target Behavior
    6. 7.6 Register Map
      1. 7.6.1 TUSB1142 Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
  9. 9 Typical Application
  10. 10Design Requirements
  11. 11Detailed Design Procedure
    1. 11.1 USB SSTX Receiver Configuration
    2. 11.2 USB CRX1/2 Receiver Configuration
      1. 11.2.1 Fixed Equalization
      2. 11.2.2 Full Adaptive Equalization
      3. 11.2.3 Fast Adaptive Equalization
  12. 12Application Curves
  13. 13Power Supply Recommendations
  14. 14Layout
    1. 14.1 Layout Guidelines
    2. 14.2 Layout Example
  15. 15Device and Documentation Support
    1. 15.1 Receiving Notification of Documentation Updates
    2. 15.2 Support Resources
    3. 15.3 Trademarks
    4. 15.4 Electrostatic Discharge Caution
    5. 15.5 Glossary
  16. 16Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.4 USB 3.2 2:1 MUX Description

The TUSB1142 implements a 2:1 MUX between the USB-C receptacle and the USB 3.2 Host, Hub or device. In pin-strap mode the selection of MUX path is controlled from the FLIP pin. In I2C mode, the MUX is controlled by FLIP_SEL register. Refer to Table 7-4 for details.

Table 7-4 USB 3.2 MUX Control

FLIP pin or FLIP_SEL register

EN pin or CTLSEL register

USB Path

X

0

Disabled

0

1

CRX1 -> SSRX

SSTX -> CTX1

1

1

CRX2 -> SSRX

SSTX -> CTX2