SLLSF07 September   2017 TUSB215-Q1


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 EQ
      2. 7.3.2 DC BOOST
      3. 7.3.3 BC1.2 CDP Support
    4. 7.4 Device Functional Modes
      1. 7.4.1 Low Speed (LS) Mode
      2. 7.4.2 Full Speed (FS) Mode
      3. 7.4.3 High Speed (HS) Mode
      4. 7.4.4 Shutdown Mode
      5. 7.4.5 I2C Mode
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. Test Procedure to Construct USB High Speed Eye Diagram
          1. For a Host Side Application
          2. For a Device Side Application
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGY|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Detailed Description


The TUSB215-Q1 is a USB High-Speed (HS) signal conditioner, designed to compensate for ISI signal loss in a transmission channel. TUSB215-Q1 has a patent-pending design which is agnostic to USB Low Speed (LS) and Full Speed (FS) signals and does not alter their signal characteristics, while HS signals are compensated. In addition, the design is compatible with USB On-The-Go (OTG) and Battery Charging (BC) specifications. The TUSB215-Q1 provides USB Charging Downstream Port (CDP) controller for applications in which USB host or hub do not have this function.

Programmable signal AC boost through an external resistor on EQ pin permits fine tuning device performance to optimize signals helping to pass USB HS electrical compliance tests at the connector. Additional DC Boost configurable by three level input DC_BOOST pin helps overcoming the cable losses.

Functional Block Diagram

TUSB215-Q1 sllsex5_fbd_tusb214_215_diagram.gif

Feature Description


The EQ pin of the TUSB215-Q1 is used to configure the AC boost of the device. The four levels of AC boost are set through different values of an external pulldown resistor at this pin.


The DC_BOOST pin of the TUSB215-Q1 is a tri-level pin, used to set the DC gain of the device according to Table 1.

Table 1. DC Boost Settings

DC_BOOST DC Boost Setting (mV)
VIL 40
VIM 60
VIH 80

BC1.2 CDP Support

The TUSB215-Q1 main function is a signal conditioner offering the EQ/Boost features to the incoming DP/DM signals. For applications in which USB host or hub do not provide USB BC charging downstream port (CDP) functionality, the TUSB215-Q1 can perform this task.

Device Functional Modes

Low Speed (LS) Mode

TUSB215-Q1 automatically detects a LS connection and does not enable signal compensation. CD pin is asserted high.

Full Speed (FS) Mode

TUSB215-Q1 automatically detects a FS connection and does not enable signal compensation. CD pin is asserted high.

High Speed (HS) Mode

TUSB215-Q1 automatically detects a HS connection and will enable signal compensation as determined by the configuration of the DC_BOOST pin and the external pulldown resistance on its EQ pin. CD pin asserted high.

Shutdown Mode

TUSB215-Q1 is disabled when its RSTN pin is asserted low. In shutdown mode, the USB channel is still fully operational but there is neither signal compensation nor any indication from the CD pin as to the status of the channel.

I2C Mode

TUSB215-Q1 support 100 kHz I2C for device configuration, status readback and test purposes. This controller is enabled after SCL and SDA pins are sampled high shortly after de-assertion of RSTN. In this mode, the register as described in Table 2 can be accessed by I2C read/write transaction to 7-bit slave address 0x2C. It is necessary to set CFG_ACTIVE bit and reset it to zero after making changes to the EQ and DC Boost level registers to restart the state machine.


All registers or fields in Table 2 which are not specifically mentioned are considered reserved. The default value of these reserved registers or fields must not be changed. It is suggested to perform a read-modify-write operation to maintain the default value of the reserved fields.

Table 2. Register definition

Offset Bit(s) Name Type Default Description
0x01 6:4 ACB_LVL RW XXX (Sampled from EQ pin at reset)

Sets the level of AC boost

000 :Level 0 AC boost programmed [MIN]

001 : Level 1 AC boost programmed

011 : Level 2 AC boost programmed

111 : Level 3 AC boost programmed [MAX]

0x03 0 CFG_ACTIVE RW 1b

Configuration mode

0 : Normal mode. State machine enabled.

1 : Configuration mode: State machine disabled.

After reset, if I2C mode is true (SCL and SDA are both pulled high) it is maintained until it is cleared by an I2C write, but, if I2C mode is not true, it is cleared automatically.

0x0E 2:0 DCB_LVL RW XXX (Sampled from DC_BOOST pin at reset)

Sets the level of DC Boost

011 : 40mV (DC_Boost = L)

101 : 60mV (DC_Boost = M, default)

111 : 80mV (DC_Boost = H)