SNLS648B February 2019 – October 2023 TUSB2E22
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
CROSS pin will control the orientation of the integrated cross bar mux.
Upon de-assertion of RESETB followed by internally generated reset signal and 1ms delay, CROSS pin is sampled and latched.
The system needs to make sure that CROSS meets t_su_CROSS and t_hd_CROSS with respect to power supply ramp and RESETB de-assertion per Section 9.3.
Changes to the state of the CROSS input while RESETB is high will be ignored.
CROSS = 0 | CROSS = 1 | |
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eUSB0 (eDP0, eDN0) | USBA (DPA, DNA) | USBB (DPB, DNB) |
eUSB1 (eDP1, eDN1) | USBB (DPB, DNB) | USBA (DPA, DNA) |