SLLS519J March   2002  – July 2017 TUSB3410

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Pin Configuration and Functions
    1. 3.1 Pin Diagrams
  4. 4Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Thermal Information
    5. 4.5 Electrical Characteristics
    6. 4.6 Timing and Switching Characteristics Information
      1. 4.6.1 Wakeup Timing (WAKEUP or RI/CP Transitions)
      2. 4.6.2 Reset Timing
    7. 4.7 Typical Characteristics
  5. 5Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 Device Functional Modes
      1. 5.3.1 USB Interface Configuration
        1. 5.3.1.1 External Memory Case
        2. 5.3.1.2 Host Download Case
      2. 5.3.2 USB Data Movement
      3. 5.3.3 Serial Port Setup
      4. 5.3.4 Serial Port Data Modes
        1. 5.3.4.1 RS-232 Data Mode
        2. 5.3.4.2 RS-485 Data Mode
        3. 5.3.4.3 IrDA Data Mode
    4. 5.4 Processor Subsystems
      1. 5.4.1 DMA Controller
        1. 5.4.1.1 Bulk Data I/O Using the EDB
          1. 5.4.1.1.1 IN Transaction (TUSB3410 to Host)
          2. 5.4.1.1.2 OUT Transaction (Host to TUSB3410)
      2. 5.4.2 UART
        1. 5.4.2.1 UART Data Transfer
          1. 5.4.2.1.1 Receiver Data Flow
          2. 5.4.2.1.2 Hardware Flow Control
          3. 5.4.2.1.3 Auto RTS (Receiver Control)
          4. 5.4.2.1.4 Auto CTS (Transmitter Control)
          5. 5.4.2.1.5 Xon/Xoff Receiver Flow Control
          6. 5.4.2.1.6 Xon/Xoff Transmit Flow Control
      3. 5.4.3 I2C Port
        1. 5.4.3.1 Random-Read Operation
          1. 5.4.3.1.1 Device Address + EPROM [High Byte]
          2. 5.4.3.1.2 EPROM [Low Byte]
        2. 5.4.3.2 Current-Address Read Operation
        3. 5.4.3.3 Sequential-Read Operation
          1. 5.4.3.3.1 Device Address
          2. 5.4.3.3.2 N-Byte Read (31 Bytes)
          3. 5.4.3.3.3 Last-Byte Read (Byte 32)
        4. 5.4.3.4 Byte-Write Operation
          1. 5.4.3.4.1 Device Address + EPROM [High Byte]
          2. 5.4.3.4.2 EPROM [Low Byte]
          3. 5.4.3.4.3 EPROM [DATA]
        5. 5.4.3.5 Page-Write Operation
          1. 5.4.3.5.1 Device Address + EPROM [High Byte]
          2. 5.4.3.5.2 EPROM [Low Byte]
          3. 5.4.3.5.3 EPROM [DATA]—31 Bytes
          4. 5.4.3.5.4 EPROM [DATA]—Last Byte
    5. 5.5 Memory
      1. 5.5.1  MCU Memory Map
      2. 5.5.2  Registers
        1. 5.5.2.1 Miscellaneous Registers
          1. 5.5.2.1.1 ROMS: ROM Shadow Configuration Register (Addr:FF90h)
          2. 5.5.2.1.2 Boot Operation (MCU Firmware Loading)
          3. 5.5.2.1.3 WDCSR: Watchdog Timer, Control, and Status Register (Addr:FF93h)
      3. 5.5.3  Buffers + I/O RAM Map
      4. 5.5.4  Endpoint Descriptor Block (EDB−1 to EDB−3)
        1. 5.5.4.1  OEPCNF_n: Output Endpoint Configuration (n = 1 to 3) (Base Addr: FF08h, FF10h, FF18h)
        2. 5.5.4.2  OEPBBAX_n: Output Endpoint X-Buffer Base Address (n = 1 to 3) (Offset 1)
        3. 5.5.4.3  OEPBCTX_n: Output Endpoint X Byte Count (n = 1 to 3) (Offset 2)
        4. 5.5.4.4  OEPBBAY_n: Output Endpoint Y-Buffer Base Address (n = 1 to 3) (Offset 5)
        5. 5.5.4.5  OEPBCTY_n: Output Endpoint Y-Byte Count (n = 1 to 3) (Offset 6)
        6. 5.5.4.6  OEPSIZXY_n: Output Endpoint X-/Y-Buffer Size (n = 1 to 3) (Offset 7)
        7. 5.5.4.7  IEPCNF_n: Input Endpoint Configuration (n = 1 to 3) (Base Addr: FF48h, FF50h, FF58h)
        8. 5.5.4.8  IEPBBAX_n: Input Endpoint X-Buffer Base Address (n = 1 to 3) (Offset 1)
        9. 5.5.4.9  IEPBCTX_n: Input Endpoint X-Byte Count (n = 1 to 3) (Offset 2)
        10. 5.5.4.10 IEPBBAY_n: Input Endpoint Y-Buffer Base Address (n = 1 to 3) (Offset 5)
        11. 5.5.4.11 IEPBCTY_n: Input Endpoint Y-Byte Count (n = 1 to 3) (Offset 6)
        12. 5.5.4.12 IEPSIZXY_n: Input Endpoint X-/Y-Buffer Size (n = 1 to 3) (Offset 7)
        13. 5.5.4.13 Endpoint-0 Descriptor Registers
          1. 5.5.4.13.1 IEPCNFG_0: Input Endpoint-0 Configuration Register (Addr:FF80h)
          2. 5.5.4.13.2 IEPBCNT_0: Input Endpoint-0 Byte Count Register (Addr:FF81h)
          3. 5.5.4.13.3 OEPCNFG_0: Output Endpoint-0 Configuration Register (Addr:FF82h)
          4. 5.5.4.13.4 OEPBCNT_0: Output Endpoint-0 Byte Count Register (Addr:FF83h)
      5. 5.5.5  USB Registers
        1. 5.5.5.1  FUNADR: Function Address Register (Addr:FFFFh)
        2. 5.5.5.2  USBSTA: USB Status Register (Addr:FFFEh)
        3. 5.5.5.3  USBMSK: USB Interrupt Mask Register (Addr:FFFDh)
        4. 5.5.5.4  USBCTL: USB Control Register (Addr:FFFCh)
        5. 5.5.5.5  MODECNFG: Mode Configuration Register (Addr:FFFBh)
        6. 5.5.5.6  Clock Output Control
        7. 5.5.5.7  Vendor ID/Product ID
        8. 5.5.5.8  SERNUM7: Device Serial Number Register (Byte 7) (Addr:FFEFh)
        9. 5.5.5.9  SERNUM6: Device Serial Number Register (Byte 6) (Addr:FFEEh)
        10. 5.5.5.10 SERNUM5: Device Serial Number Register (Byte 5) (Addr:FFEDh)
        11. 5.5.5.11 SERNUM4: Device Serial Number Register (Byte 4) (Addr:FFECh)
        12. 5.5.5.12 SERNUM3: Device Serial Number Register (Byte 3) (Addr:FFEBh)
        13. 5.5.5.13 SERNUM2: Device Serial Number Register (Byte 2) (Addr:FFEAh)
        14. 5.5.5.14 SERNUM1: Device Serial Number Register (Byte 1) (Addr:FFE9h)
        15. 5.5.5.15 SERNUM0: Device Serial Number Register (Byte 0) (Addr:FFE8h)
        16. 5.5.5.16 Function Reset and Power-Up Reset Interconnect
        17. 5.5.5.17 Pullup Resistor Connect and Disconnect
      6. 5.5.6  DMA Controller Registers
        1. 5.5.6.1 DMACDR1: DMA Channel Definition Register (UART Transmit Channel) (Addr:FFE0h)
        2. 5.5.6.2 DMACSR1: DMA Control And Status Register (UART Transmit Channel) (Addr:FFE1h)
        3. 5.5.6.3 DMACDR3: DMA Channel Definition Register (UART Receive Channel) (Addr:FFE4h)
        4. 5.5.6.4 DMACSR3: DMA Control And Status Register (UART Receive Channel) (Addr:FFE5h)
      7. 5.5.7  UART Registers
        1. 5.5.7.1  RDR: Receiver Data Register (Addr:FFA0h)
        2. 5.5.7.2  TDR: Transmitter Data Register (Addr:FFA1h)
        3. 5.5.7.3  LCR: Line Control Register (Addr:FFA2h)
        4. 5.5.7.4  FCRL: UART Flow Control Register (Addr:FFA3h)
        5. 5.5.7.5  Transmitter Flow Control
        6. 5.5.7.6  MCR: Modem-Control Register (Addr:FFA4h)
        7. 5.5.7.7  LSR: Line-Status Register (Addr:FFA5h)
        8. 5.5.7.8  MSR: Modem-Status Register (Addr:FFA6h)
        9. 5.5.7.9  DLL: Divisor Register Low Byte (Addr:FFA7h)
        10. 5.5.7.10 DLH: Divisor Register High Byte (Addr:FFA8h)
        11. 5.5.7.11 Baud-Rate Calculation
        12. 5.5.7.12 XON: Xon Register (Addr:FFA9h)
        13. 5.5.7.13 XOFF: Xoff Register (Addr:FFAAh)
        14. 5.5.7.14 MASK: UART Interrupt-Mask Register (Addr:FFABh)
      8. 5.5.8  Expanded GPIO Port
        1. 5.5.8.1 Input/Output and Control Registers
          1. 5.5.8.1.1 PUR_3: GPIO Pullup Register for Port 3 (Addr:FF9Eh)
      9. 5.5.9  Interrupts
        1. 5.5.9.1 8052 Interrupt and Status Registers
          1. 5.5.9.1.1 8052 Standard Interrupt Enable (SIE) Register
          2. 5.5.9.1.2 Additional Interrupt Sources
          3. 5.5.9.1.3 VECINT: Vector Interrupt Register (Addr:FF92h)
          4. 5.5.9.1.4 Logical Interrupt Connection Diagram (Internal/External)
      10. 5.5.10 I2C Registers
        1. 5.5.10.1 I2CSTA: I2C Status and Control Register (Addr:FFF0h)
        2. 5.5.10.2 I2CADR: I2C Address Register (Addr:FFF3h)
        3. 5.5.10.3 I2CDAI: I2C Data-Input Register (Addr:FFF2h)
        4. 5.5.10.4 I2CDAO: I2C Data-Output Register (Addr:FFF1h)
    6. 5.6 Boot Modes
      1. 5.6.1  Introduction
      2. 5.6.2  Bootcode Programming Flow
      3. 5.6.3  Default Bootcode Settings
        1. 5.6.3.1 Device Descriptor
        2. 5.6.3.2 Configuration Descriptor
        3. 5.6.3.3 Interface Descriptor
        4. 5.6.3.4 Endpoint Descriptor
        5. 5.6.3.5 String Descriptor
      4. 5.6.4  External I2C Device Header Format
        1. 5.6.4.1 Product Signature
        2. 5.6.4.2 Descriptor Block
          1. 5.6.4.2.1 Descriptor Prefix
          2. 5.6.4.2.2 Descriptor Content
      5. 5.6.5  Checksum in Descriptor Block
      6. 5.6.6  Header Examples
        1. 5.6.6.1 TUSB3410 Bootcode Supported Descriptor Block
        2. 5.6.6.2 USB Descriptor Header
        3. 5.6.6.3 Autoexec Binary Firmware
      7. 5.6.7  USB Host Driver Downloading Header Format
      8. 5.6.8  Built-In Vendor Specific USB Requests
        1. 5.6.8.1 Reboot
        2. 5.6.8.2 Force Execute Firmware
        3. 5.6.8.3 External Memory Read
        4. 5.6.8.4 External Memory Write
        5. 5.6.8.5 I2C Memory Read
        6. 5.6.8.6 I2C Memory Write
        7. 5.6.8.7 Internal ROM Memory Read
      9. 5.6.9  Bootcode Programming Consideration
        1. 5.6.9.1 USB Requests
          1. 5.6.9.1.1 USB Request Transfers
          2. 5.6.9.1.2 Interrupt Handling Routine
        2. 5.6.9.2 Hardware Reset Introduced by the Firmware
      10. 5.6.10 File Listings
  6. 6Application, Implementation, and Layout
    1. 6.1 Application Information
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
        1. 6.2.2.1 Upstream Port Implementation
        2. 6.2.2.2 Crystal Implementation
        3. 6.2.2.3 RS-232 Implementation
        4. 6.2.2.4 TUSB3410 Power Implementation
      3. 6.2.3 Application Performance Plot
    3. 6.3 Layout
      1. 6.3.1 Layout Guidelines
      2. 6.3.2 Differential Signal Spacing
      3. 6.3.3 Differential Signal Rules
      4. 6.3.4 Layout Example
    4. 6.4 Power Supply Recommendations
      1. 6.4.1 Digital Supplies 3.3 V
      2. 6.4.2 Digital Supplies 1.8 V
    5. 6.5 Crystal Selection
    6. 6.6 External Circuit Required for Reliable Bus Powered Suspend Operation
  7. 7Device and Documentation Support
    1. 7.1 Documentation Support
      1. 7.1.1 Related Documentation
    2. 7.2 Related Links
    3. 7.3 Receiving Notification of Documentation Updates
    4. 7.4 Community Resources
    5. 7.5 Trademarks
    6. 7.6 Electrostatic Discharge Caution
    7. 7.7 Glossary
  8. 8Mechanical Packaging and Orderable Information
    1. 8.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Device and Documentation Support

7.1 Documentation Support

7.1.1 Related Documentation

For related documentation, see the following:

    SLLS178 SN75LV4737A 3.3-V/5-V Multichannel RS-232 Line Driver/Receiver

7.2 Related Links

The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy.

Table 7-1 Related Links

PARTS PRODUCT FOLDER ORDER NOW TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY
TUSB3410 Click here Click here Click here Click here Click here
TUSB3410I Click here Click here Click here Click here Click here

7.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

7.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

    TI E2E™ Online Community The TI engineer-to-engineer (E2E) community was created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers.
    Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

7.5 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

7.6 Electrostatic Discharge Caution

esds-image

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

7.7 Glossary

    TI Glossary This glossary lists and explains terms, acronyms, and definitions.