SLLSEK4B July   2015  – January 2016 TUSB4041I-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 3.3-V I/O Electrical Characteristics
    6. 7.6 Power-Up Timing Requirements
    7. 7.7 Hub Input Supply Current
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Battery Charging Features
      2. 8.3.2 USB Power Management
      3. 8.3.3 One-Time Programmable Configuration
      4. 8.3.4 Clock Generation
      5. 8.3.5 Crystal Requirements
      6. 8.3.6 Input Clock Requirements
      7. 8.3.7 Power-Up and Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 External Configuration Interface
      2. 8.4.2 I2C EEPROM Operation
      3. 8.4.3 SMBus Slave Operation
    5. 8.5 Register Maps
      1. 8.5.1  Configuration Registers
      2. 8.5.2  ROM Signature Register
      3. 8.5.3  Vendor ID LSB Register
      4. 8.5.4  Vendor ID MSB Register
      5. 8.5.5  Product ID LSB Register
      6. 8.5.6  Product ID MSB Register
      7. 8.5.7  Device Configuration Register
      8. 8.5.8  Battery Charging Support Register
      9. 8.5.9  Device Removable Configuration Register
      10. 8.5.10 Port Used Configuration Register
      11. 8.5.11 Device Configuration Register 2
      12. 8.5.12 USB 2.0 Port Polarity Control Register
      13. 8.5.13 UUID Byte N Register
      14. 8.5.14 Language ID LSB Register
      15. 8.5.15 Language ID MSB Register
      16. 8.5.16 Serial Number String Length Register
      17. 8.5.17 Manufacturer String Length Register
      18. 8.5.18 Product String Length Register
      19. 8.5.19 Serial Number String Registers
      20. 8.5.20 Manufacturer String Registers
      21. 8.5.21 Product String Byte N Register
      22. 8.5.22 Additional Feature Configuration Register
      23. 8.5.23 Device Status and Command Register
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Upstream Port Implementation
        2. 9.2.2.2 Downstream Port 1 Implementation
        3. 9.2.2.3 Downstream Port 2 Implementation
        4. 9.2.2.4 Downstream Port 3 Implementation
        5. 9.2.2.5 Downstream Port 4 Implementation
        6. 9.2.2.6 VBUS Power Switch Implementation
        7. 9.2.2.7 Clock, Reset, and Miscellaneous
        8. 9.2.2.8 TUSB4041I-Q1 Power Implementation
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 TUSB4041I-Q1 Power Supply
    2. 10.2 Downstream Port Power
    3. 10.3 Ground
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Placement
      2. 11.1.2 Package Specific
      3. 11.1.3 Differential Pairs
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Community Resource
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage VDD steady-state supply voltage –0.3 1.4 V
VDD33 steady-state supply voltage –0.3 3.8 V
Voltage USB_VBUS pin –0.3 1.4 V
XI pins –0.3 2.45 V
All other pins –0.3 3.8 V
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed as Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated as Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±2000 V
Charged-device model (CDM), per AEC Q100-011 ±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDD(1) 1.1-V supply voltage 0.99 1.1 1.26 V
VDD33 3.3-V supply voltage 3 3.3 3.6 V
V(USB_VBUS) Voltage at USB_VBUS pin 0 1.155 V
TA Operating free-air temperature –40 85 °C
TJ Operating junction temperature –40 105 °C
(1) A 1.05-V, 1.1-V, or 1.2-V supply may be used as long as minimum and maximum supply conditions are met.

7.4 Thermal Information

THERMAL METRIC(1) TUSB4041I-Q1 UNIT
PAP (HTQFP)
64 PINS
RθJA Junction-to-ambient thermal resistance 26.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 11.5 °C/W
RθJB Junction-to-board thermal resistance 10.4 °C/W
ψJT Junction-to-top characterization parameter 0.2 °C/W
ψJB Junction-to-board characterization parameter 10.3 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.6 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 3.3-V I/O Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER OPERATION TEST CONDITIONS MIN TYP MAX UNIT
VIH High-level input voltage(1) VDD33 2 VDD33 V
VIL Low-level input voltage(1) VDD33 JTAG pins only 0 0.55 V
Other pins 0 0.8
VI Input voltage 0 VDD33 V
VO Output voltage(2) 0 VDD33 V
tt Input transition time (tr and tf) 0 25 ns
Vhys Input hysteresis(3) 0.13 x VDD33 V
VOH High-level output voltage VDD33 IOH = –4 mA 2.4 V
VOL Low-level output voltage VDD33 IOL = 4 mA 0.4 V
IOZ High-impedance, output current(2) VDD33 VI = 0 to VDD33 ±20 µA
IOZ(P) High-impedance, output current with internal pullup or pulldown resistor(4) VDD33 VI = 0 to VDD33 ±250 µA
II Input current(5) VDD33 VI = 0 to VDD33 ±15 µA
(1) Applies to external inputs and bidirectional buffers.
(2) Applies to external outputs and bidirectional buffers.
(3) Applies to GRSTz.
(4) Applies to pins with internal pull-ups and pull-downs.
(5) Applies to external input buffers.

7.6 Power-Up Timing Requirements

MIN NOM MAX UNIT
td1 VDD33 stable before VDD stable(1) See (2) ms
td2 VDD and VDD33 stable before deassertion of GRSTz 3 ms
tsu_io Setup for MISC inputs(3) sampled at the deassertion of GRSTz 0.1 µs
thd_io Hold for MISC inputs(3) sampled at the deassertion of GRSTz 0.1 µs
tVDD33_RAMP VDD33 supply ramp requirements 0.2 100 ms
tVDD_RAMP VDD supply ramp requirements 0.2 100 ms
(1) An active reset is required if the VDD33 supply is stable before the VDD11 supply. This active Reset shall meet the 3ms power-up delay counting from both power supplies being stable to the de-assertion of GRSTz.
(2) The VDD33 and VDD have no power-on relationship unless GRSTz is only connected to a capacitor to GND. Then VDD must be stable minimum of 10 μs before the VDD33.
(3) MISC pins sampled at de-assertion of GRSTz: FULLPWRMGMTz, GANGED, PWRCTL_POL, SMBUSz, BATEN[4:1], and AUTOENz.
TUSB4041I-Q1 pwr_up_timing_sllsee4.gif Figure 1. Power-Up Timing Requirements

7.7 Hub Input Supply Current

Typical values measured at TA = 25°C
PARAMETER VDD33 VDD UNIT
3.3 V 1.1 V
LOW POWER MODES
Power on (after reset)                    2.3 28 mA
Upstream disconnect 2.3 28 mA
Suspend                                   2.5 33 mA
ACTIVE MODES (US STATE AND DS STATE)
2.0 host / 1 HS device 45 63 mA
2.0 host / 4 HS devices 76 86 mA