SLLSEK3E July   2015  – September 2017 TUSB4041I

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 3.3-V I/O Electrical Characteristics
    6. 7.6 Power-Up Timing Requirements
    7. 7.7 Hub Input Supply Current
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Battery Charging Features
      2. 8.3.2 USB Power Management
      3. 8.3.3 One-Time Programmable Configuration
      4. 8.3.4 Clock Generation
      5. 8.3.5 Crystal Requirements
      6. 8.3.6 Input Clock Requirements
      7. 8.3.7 Power-Up and Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 External Configuration Interface
      2. 8.4.2 I2C EEPROM Operation
      3. 8.4.3 SMBus Slave Operation
    5. 8.5 Register Maps
      1. 8.5.1  Configuration Registers
      2. 8.5.2  ROM Signature Register
      3. 8.5.3  Vendor ID LSB Register
      4. 8.5.4  Vendor ID MSB Register
      5. 8.5.5  Product ID LSB Register
      6. 8.5.6  Product ID MSB Register
      7. 8.5.7  Device Configuration Register
      8. 8.5.8  Battery Charging Support Register
      9. 8.5.9  Device Removable Configuration Register
      10. 8.5.10 Port Used Configuration Register
      11. 8.5.11 Device Configuration Register 2
      12. 8.5.12 USB 2.0 Port Polarity Control Register
      13. 8.5.13 UUID Byte N Register
      14. 8.5.14 Language ID LSB Register
      15. 8.5.15 Language ID MSB Register
      16. 8.5.16 Serial Number String Length Register
      17. 8.5.17 Manufacturer String Length Register
      18. 8.5.18 Product String Length Register
      19. 8.5.19 Serial Number String Registers
      20. 8.5.20 Manufacturer String Registers
      21. 8.5.21 Product String Byte N Register
      22. 8.5.22 Additional Feature Configuration Register
      23. 8.5.23 Device Status and Command Register
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Upstream Port Implementation
        2. 9.2.2.2 Downstream Port 1 Implementation
        3. 9.2.2.3 Downstream Port 2 Implementation
        4. 9.2.2.4 Downstream Port 3 Implementation
        5. 9.2.2.5 Downstream Port 4 Implementation
        6. 9.2.2.6 VBUS Power Switch Implementation
        7. 9.2.2.7 Clock, Reset, and Miscellaneous
        8. 9.2.2.8 TUSB4041I Power Implementation
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 TUSB4041I Power Supply
    2. 10.2 Downstream Port Power
    3. 10.3 Ground
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Placement
      2. 11.1.2 Package Specific
      3. 11.1.3 Differential Pairs
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resource
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PAP|64
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The TUSB4041I device is a four-port USB 2.0 hub. The provides USB high-speed and full-speed connections on the upstream port and provides USB high-speed, full-speed, or low-speed connections on the downstream port. The TUSB4041I device can be used in any application that requires additional USB-compliant ports. For example, a specific notebook may only have two downstream USB ports. By using the TUSB4041I device, the notebook can increase the downstream port count to five.

9.2 Typical Application

A common application for the TUSB4041I device is as a self-powered standalone USB-hub product. The product is powered by an external 5-V DC power adapter. In this application, using a USB cable, the upstream port of the TUSB4041I device is plugged into a USB host controller. The downstream ports of the TUSB4041I device are exposed to users for connecting USB hard drives, cameras, flash drives, and so forth.

TUSB4041I TUSB4041I_TypApp_SLLSEK3.gif Figure 25. Discrete USB Hub Product

9.2.1 Design Requirements

For this design example, use the parameters listed in Table 26.

Table 26. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
VDD supply 1.1 V
VDD33 supply 3.3 V
Upstream port USB support (HS, FS) HS, FS
Downstream port 1 USB support (HS, FS, LS) HS, FS, LS
Downstream port 2 USB support (HS, FS, LS) HS, FS, LS
Downstream port 3 USB support (HS, FS, LS) HS, FS, LS
Downstream port 4 USB support (HS, FS, LS) HS, FS, LS
Number of removable downstream ports 4
Number of non-removable downstream ports 0
Full power management of downstream ports Yes (FULLPWRMGMTZ = 0)
Individual control of downstream port power switch Yes (GANGED = 0)
Power switch enable polarity Active high (PWRCTL_POL = 1)
Battery charge support for downstream port 1 Yes
Battery charge support for downstream port 2 Yes
Battery charge support for downstream port 3 Yes
Battery charge support for downstream port 4 Yes
I2C EEPROM support No
24-MHz clock source Crystal

9.2.2 Detailed Design Procedure

9.2.2.1 Upstream Port Implementation

TUSB4041I TUSB4041IQ1_USP_SLLSEK4.gif Figure 26. Upstream Port Implementation

The upstream of the TUSB4041I device is connected to a USB2 Type B connector. This particular example has GANGED pin and FULLPWRMGMTZ pin pulled low, which results in individual power support each downstream port. The VBUS signal from the USB2 Type B connector is feed through a voltage divider. The purpose of the voltage divider is to make sure the level meets USB_VBUS input requirements

9.2.2.2 Downstream Port 1 Implementation

TUSB4041I TUSB4041IQ1_DS1_SLLSEK4.gif Figure 27. Downstream Port 1 Implementation

The downstream port 1 of the TUSB4041I device is connected to a USB2 type A connector. With BATEN1 pin pulled up, battery charge support is enabled for Port 1. If battery charge support is not needed, then uninstall the pullup resistor on BATEN1.

9.2.2.3 Downstream Port 2 Implementation

TUSB4041I TUSB4041IQ1_DS2_SLLSEK4.gif Figure 28. Downstream Port 2 Implementation

The downstream port 2 of the TUSB4041I device is connected to a USB2 type A connector. With BATEN2 pin pulled up, battery charge support is enabled for port 2. If battery charge support is not needed, then uninstall the pullup resistor on BATEN2.

9.2.2.4 Downstream Port 3 Implementation

TUSB4041I TUSB4041IQ1_DS3_SLLSEK4.gif Figure 29. Downstream Port 3 Implementation

The downstream port3 of the TUSB4041I device is connected to a USB2 type A connector. With BATEN3 pin pulled up, battery charge support is enabled for port 3. If battery charge support is not needed, then uninstall the pullup resistor on BATEN3.

9.2.2.5 Downstream Port 4 Implementation

TUSB4041I TUSB4041IQ1_DS4_SLLSEK4.gif Figure 30. Downstream Port 4 Implementation

The downstream port 4 of the TUSB4041I device is connected to a USB2 Type A connector. With BATEN4 pin pulled up, Battery Charge support is enabled for Port 4. If Battery Charge support is not needed, then uninstall the pullup resistor on BATEN4.

9.2.2.6 VBUS Power Switch Implementation

TUSB4041I vbus_imp_sllsek4.gif Figure 31. VBUS Power Switch Implementation

This particular example uses TI's TPS2561 dual-channel precision adjustable current-limited power switch. For details on this power switch or other power switches available from TI, refer to www.ti.com.

9.2.2.7 Clock, Reset, and Miscellaneous

The PWRCTL_POL is left unconnected which results in active-high power enable (PWRCTL1, PWRCTL2, PWRCTL3, and PWRCTL4) for a USB VBUS power switch. The 1-µF capacitor on the GRSTN pin can only be used if the VDD11 supply is stable before the VDD33 supply. Depending on the supply ramp of the two supplies, the user may need to adjust the capacitor.

TUSB4041I TUSB4041IQ1_MISC_SLLSEK4.gif Figure 32. Clock, Reset, and Miscellaneous

9.2.2.8 TUSB4041I Power Implementation

TUSB4041I TUSB4041IQ1_PWR_SLLSEK4.gif Figure 33. TUSB4041I Power Implementation

9.2.3 Application Curves

TUSB4041I eye_hs_us_sllsee4.gif
Figure 34. High-Speed Upstream Port
TUSB4041I eye_hs_ds2_sllsee4.gif
Figure 36. High-Speed Downstream Port 2
TUSB4041I eye_hs_ds4_sllsee4.gif
Figure 38. High-Speed Downstream Port 4
TUSB4041I eye_hs_ds1_sllsee4.gif
Figure 35. High-Speed Downstream Port 1
TUSB4041I eye_hs_ds3_sllsee4.gif
Figure 37. High-Speed Downstream Port 3