SLLSEK3E July   2015  – September 2017 TUSB4041I

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 3.3-V I/O Electrical Characteristics
    6. 7.6 Power-Up Timing Requirements
    7. 7.7 Hub Input Supply Current
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Battery Charging Features
      2. 8.3.2 USB Power Management
      3. 8.3.3 One-Time Programmable Configuration
      4. 8.3.4 Clock Generation
      5. 8.3.5 Crystal Requirements
      6. 8.3.6 Input Clock Requirements
      7. 8.3.7 Power-Up and Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 External Configuration Interface
      2. 8.4.2 I2C EEPROM Operation
      3. 8.4.3 SMBus Slave Operation
    5. 8.5 Register Maps
      1. 8.5.1  Configuration Registers
      2. 8.5.2  ROM Signature Register
      3. 8.5.3  Vendor ID LSB Register
      4. 8.5.4  Vendor ID MSB Register
      5. 8.5.5  Product ID LSB Register
      6. 8.5.6  Product ID MSB Register
      7. 8.5.7  Device Configuration Register
      8. 8.5.8  Battery Charging Support Register
      9. 8.5.9  Device Removable Configuration Register
      10. 8.5.10 Port Used Configuration Register
      11. 8.5.11 Device Configuration Register 2
      12. 8.5.12 USB 2.0 Port Polarity Control Register
      13. 8.5.13 UUID Byte N Register
      14. 8.5.14 Language ID LSB Register
      15. 8.5.15 Language ID MSB Register
      16. 8.5.16 Serial Number String Length Register
      17. 8.5.17 Manufacturer String Length Register
      18. 8.5.18 Product String Length Register
      19. 8.5.19 Serial Number String Registers
      20. 8.5.20 Manufacturer String Registers
      21. 8.5.21 Product String Byte N Register
      22. 8.5.22 Additional Feature Configuration Register
      23. 8.5.23 Device Status and Command Register
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Upstream Port Implementation
        2. 9.2.2.2 Downstream Port 1 Implementation
        3. 9.2.2.3 Downstream Port 2 Implementation
        4. 9.2.2.4 Downstream Port 3 Implementation
        5. 9.2.2.5 Downstream Port 4 Implementation
        6. 9.2.2.6 VBUS Power Switch Implementation
        7. 9.2.2.7 Clock, Reset, and Miscellaneous
        8. 9.2.2.8 TUSB4041I Power Implementation
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 TUSB4041I Power Supply
    2. 10.2 Downstream Port Power
    3. 10.3 Ground
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Placement
      2. 11.1.2 Package Specific
      3. 11.1.3 Differential Pairs
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resource
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PAP|64
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Layout

11.1 Layout Guidelines

Use the layout guidelines listed in this section for proper PCB layout design.

11.1.1 Placement

  • Place a 9.53-kΩ ±1% resistor connected to pin USB_R1 as close as possible to the TUSB4041I device.
  • Place a 0.1-µF capacitor as close as possible on each VDD and VDD33 power pin.
  • The ESD and EMI protection devices (if used) should also be placed as close as possible to the USB connector.
  • If a crystal is used, it must be placed as close as possible to the XI and XO pins of the TUSB4041I device.
  • Place voltage regulators as far away as possible from the TUSB4041I device, the crystal, and the differential pairs.
  • In general, the user should place the large bulk capacitors associated with each power rail as close as possible to the voltage regulators.

11.1.2 Package Specific

  • The TUSB4041I device package has a 0.5-mm pin pitch.
  • The TUSB4041I device package has a 4.64-mm × 4.64-mm thermal pad. This thermal pad must be connected to ground through a system of vias.
  • Solder mask all vias under device, except for those connected to the thermal pad, to avoid any potential issues with thermal pad layouts.

11.1.3 Differential Pairs

This section describes the layout recommendations for all the TUSB4041I device differential pairs: USB_DP_XX, USB_DM_XX.

  • The differential pairs must be designed with a differential impedance of 90 Ω ± 10%.
  • To minimize crosstalk, TI recommends to keep high-speed signals away from each other. Each pair should be separated by at least 5 times the signal trace width. Separating with ground as depicted in the layout example also helps minimize crosstalk.
  • Route all differential pairs on the same layer adjacent to a solid ground plane.
  • Do not route differential pairs over any plane split.
  • Adding test points causes impedance discontinuity and therefore negatively impacts signal performance. If test points are used, place them in series and symmetrically. Do not place them in a manner that causes stub on the differential pair.
  • Avoid 90° turns in trace. Keep the use of bends in differential traces to a minimum. When bends are used, the number of left and right bends should be as equal as possible and the angle of the bend should be ≥135°. This guideline minimizes any length mismatch caused by the bends and therefore minimize the impact bends have on EMI.
  • Minimize the trace lengths of the differential pair traces. Eight inches is the maximum recommended trace length for USB 2.0 differential pair signals. Longer trace lengths require very careful routing to assure proper signal integrity.
  • Match the etch lengths of the differential pair traces (that is DP and DM). The USB 2.0 differential pairs should not exceed 50 mils relative trace length difference.
  • Minimize the use of vias in the differential pair paths as much as possible. If this is not practical, make sure that the same via type and placement are used for both signals in a pair. Place any vias used as close as possible to the TUSB4041I device.
  • To ease routing of the USB 2.0 DP and DM pair, the polarity of these pins can be swapped. If this is done, set the appropriate Px_usb2pol register, where x = 0, 1, 2, 3, or 4.
  • Do not place power fuses across the differential pair traces.

11.2 Layout Example

TUSB4041I TUSB4041IQ1_USP_LAYOUT_SLLSEK4.gif Figure 39. Example Routing of Upstream Port
TUSB4041I TUSB4041IQ1_DSP_LAYOUT_SLLSEK4.gif Figure 40. Example Routing of Downstream Port