SLLSE76Q March 2011 – March 2024 TUSB7320 , TUSB7340
PRODUCTION DATA
The Device Status Register controls PCI Express device specific parameters.
PCI register offset: 7Ah
Register type: Read Only, Clear by a Write of One, Hardware Update
Default value: 00x0h
Bit No. | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reset State | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | x | 0 | 0 | 0 | 0 |
BIT | FIELD NAME | ACCESS | DESCRIPTION |
---|---|---|---|
15:6 | RSVD | r | Reserved. Return zeros when read. |
5 | PEND | ru | Transaction Pending. |
4 | APD | ru | AUX Power Detected. This bit indicates that AUX power is present. 0 – No AUX power detected. (AUX_DET pin is 0) 1 – AUX power detected. (AUX_DET pin is 1) This bit is set based upon the state of the AUX_DET pin. |
3 | URD | rcu | Unsupported Request Detected. |
2 | FED | rcu | Fatal Error Detected. |
1 | NFED | rcu | Non-Fatal Error Detected. |
0 | CED | rcu | Correctable Error Detected. |