SLLSE76 Data sheet

SLLSE76Q March 2011 – March 2024 TUSB7320 , TUSB7340

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

RKM|100
- MPQF258B

Thermal pad, mechanical data (Package|Pins)

RKM|100
- QFND273C

Orderable Information

8.2.8 Correctable Error Mask Register

The Correctable Error Status Register reports the status of individual errors as they occur. Software may clear these bits only by writing a 1 to the desired location.

PCI Express Extended Register Offset: 114h

Default value: 0000 2000h

Table 8-118 PCI Express Extended Register 114h

Bit No.	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Reset State	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

Bit No.	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Reset State	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0

Table 8-119 Bit Descriptions – Correctable Error Mask Register

BIT	FIELD NAME	ACCESS	DESCRIPTION
31:14	RSVD	r	Reserved. Returns zeros when read.
13	ANFEM⁽¹⁾	rw	Advisory Non-Fatal Error Mask. 0 – Error Condition is Unmasked 1 – Error Condition is Masked
12	REPLAY_TMOUT_MASK⁽¹⁾	rw	Replay Timer Timeout Mask. 0 – Error Condition is Unmasked 1 – Error Condition is Masked
11:9	RSVD	r	Reserved. Returns zeros when read.
8	REPLAY_ROLL_MASK⁽¹⁾	rw	REPLAY_NUM Rollover Mask. 0 – Error Condition is Unmasked 1 – Error Condition is Masked
7	BAD_DLLP_MASK⁽¹⁾	rw	Bad DLLP Error Mask. 0 – Error Condition is Unmasked 1 – Error Condition is Masked
6	BAD_TLP_MASK⁽¹⁾	rw	Bad TLP Error Mask. 0 – Error Condition is Unmasked 1 – Error Condition is Masked
5:1	RSVD	r	Reserved. Returns zeros when read.
0	RX_ERROR_MASK⁽¹⁾	rw	Receiver Error Mask. 0 – Error Condition is Unmasked 1 – Error Condition is Masked

(1) This bit is reset by a PCI Express reset (PERST), a GRST, or the internally generated power-on-reset.