SLLSE76 Data sheet

SLLSE76Q March 2011 – March 2024 TUSB7320 , TUSB7340

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

RKM|100
- MPQF258B

Thermal pad, mechanical data (Package|Pins)

RKM|100
- QFND273C

Orderable Information

8.3.3.9 Port Status and Control Register

The TUSB73X0 implements a Port Status and Control Register for each port that is implemented. The number of Port Status and Control Registers is the same as the value in the MAX_PORTS field in the Host Controller Structural Parameters 1 Register (see Host Controller Structural Parameters 1).

Operational Base register offset: 400h + (10h × (n-1))), where n = Port Number

Default value: X000 02A0h

Table 8-157 HC Operational Register (Operational Base + 400h + (10h × (n-1))), where n = Port Number

Bit No.	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Reset State	0	x	0	0	0	0	0	0	0	0	0	0	0	0	0	0

Bit No.	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Reset State	0	0	0	0	0	0	1	0	1	0	1	0	0	0	0	0

Table 8-158 Port Status and Control Register Description

BIT	FIELD NAME	ACCESS	DESCRIPTION
31	WPR⁽¹⁾	rc or r	Warm Port Reset. This field is only valid for USB 3.0 protocol ports. For USB 2.0 protocol ports, this bit is reserved.
30	DR	r	Device Removable. The value of this bit depends on the value programmed into the USBx_PORTy_NON_REM bit in the USB Control Register that corresponds to the port number and port type associated with this register.
29:28	RSVD	r	Reserved. Returns zeros when read.
27	WOE⁽¹⁾	rw	Wake on Overcurrent Enable.
26	WDE⁽¹⁾	rw	Wake on Disconnect Enable.
25	WCE⁽¹⁾	rw	Wake on Connect Enable.
24	RSVD	r	Reserved. Return zero when read.
23	CEC⁽¹⁾	rc or r	Port Config Error Change. This field is only valid for USB 3.0 protocol ports. For USB 2.0 protocol ports, this bit is reserved.
22	PLC⁽¹⁾	rc	Port Link State Change.
21	PRC⁽¹⁾	rc	Port Reset Change.
20	OCC⁽¹⁾	rc	Overcurrent Change.
19	WRC⁽¹⁾	rc or r	Warm Port Reset Change. This field is only valid for USB 3.0 protocol ports. For USB 2.0 protocol ports, this bit is reserved.
18	PEC⁽¹⁾	rc	Port Enabled/Disabled Change.
17	CSC⁽¹⁾	rc	Connect Status Change.
16	LWS	w	Port Link State Write Strobe. This bit returns a zero when read.
15:14	PIC⁽¹⁾	rw	Port Indicator Control. Because the TUSB73X0 does not support port indicators, this field has no effect.
13:10	PORT_SPEED⁽¹⁾	r	Port Speed
9	PP⁽¹⁾	rw	Port Power.
8:5	PLS⁽¹⁾	rw	Port Link State
4	PR⁽¹⁾	rs	Port Reset.
3	OCA	r	Overcurrent Active.
2	RSVD	r	Reserved. Returns zero when read.
1	PED⁽¹⁾	rc	Port Enabled/Disabled.
0	CCS⁽¹⁾	r	Current Connect Status.

(1) This bit is a sticky bit and is reset by a global reset (GRST) or the internally-generated power-on-reset.