SCES989 May   2025 TXG8041 , TXG8042

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Supply Current
    7. 5.7  Switching Characteristics, VCCA = 1.8 ± 0.15V
    8. 5.8  Switching Characteristics, VCCA = 2.5 ± 0.2V
    9. 5.9  Switching Characteristics, VCCA = 3.3 ± 0.3V
    10. 5.10 Switching Characteristics, VCCA = 5.0 ± 0.5V
    11. 5.11 Switching Characteristics: Tsk, TMAX
    12. 5.12 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Load Circuit and Voltage Waveforms
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 CMOS Schmitt-Trigger Inputs with Integrated Pulldowns
        1. 7.3.1.1 Inputs with Integrated Static Pull-Down Resistors
      2. 7.3.2 Balanced High-Drive CMOS Push-Pull Outputs
      3. 7.3.3 VCC Disconnect
      4. 7.3.4 Over-Voltage Tolerant Inputs
      5. 7.3.5 Glitch-Free Power Supply Sequencing
      6. 7.3.6 Negative Clamping Diodes
      7. 7.3.7 Fully Configurable Dual-Rail Design
      8. 7.3.8 Supports High-Speed Translation
      9. 7.3.9 AC Noise Rejection
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Regulatory Requirements
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The TXG804x is a 4-bit, fixed direction, non-galvanic based voltage and ground-level translator that supports both logic-level shifting between 1.71V to 5.5V and ground-level shifting up to ±80V. Compared to traditional level shifters, the TXG804x family solves the challenges of voltage translation across different ground levels. The Simplified Diagram shows a common use case where DC shift occurs between GNDA to GNDB due to parasitic resistance or capacitance.

VCCA is referenced to GNDA and VCCB is referenced to GNDB. Ax pins are referenced to VCCA logic level while Bx pins are referenced to VCCB logic levels. Both A port and B port accept voltages from 1.71V to 5.5V. This device includes two enable pins that place the respective outputs in a high-impedance state when the OE pin is connected to GND or left floating. In the event of input power or signal loss, the output is default low when OE is High (refer to Table 7-1). The leakage between GNDA and GNDB is 70nA when VCC to GND is shorted.

The TXG804x device helps improve noise immunity and power sequencing across different ground domains while providing low power consumption, latency, and channel-to-channel skew. TXG804x supresses noise levels of 140PP up to 1MHz (Figure 7-3). This device supports multiple interfaces such as SPI, UART, GPIO, and I2S.

Package Information
PART NUMBERPACKAGE (1)BODY SIZE (NOM)
TXG8041

TXG8042

DYY (SOT-14)4.20mm × 2.00mm
DBQ (QSOP-16)4.90mm x 3.90mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.