SLUSDD4B April   2019  – December 2020 UC1843B-SP


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 UVLO
      2. 7.3.2 Reference
      3. 7.3.3 Totem-Pole Output
    4. 7.4 Device Functional Modes
  8. Application Information Disclaimer
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. Switching Frequency
        2. Transformer
        3. RCD Diode Clamp
        4. Output Diode
        5. Output Filter and Capacitor
        6. Compensation
        7. Sense Resistor and Slope Compensation
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Feedback Traces
      2. 10.1.2 Input/Output Capacitors
      3. 10.1.3 Compensation Components
      4. 10.1.4 Traces and Ground Planes
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Totem-Pole Output

The UC1843B-SP PWM has a single totem-pole output which can be operated to ±1-A peak for driving MOSFET gates, and a 200-mA average current for bipolar power U-100A transistors. Cross conduction between the output transistors is minimal, the average added power with VIN = 30 V is only 80 mW at 200 kHz.

Limiting the peak current through the IC is accomplished by placing a resistor between the totem-pole output and the gate of the MOSFET. The value is determined by dividing the totem-pole collector voltage VC by the peak current rating of the IC’s totem-pole. Without this resistor, the peak current is limited only by the dV/dT rate of the totem-pole switching and the FET gate capacitance. Adding resistance will increase the switching losses of the converter, but will often reducing ringing and switching noise.

The use of a Schottky diode from the PWM output to ground prevents the output voltage from going excessively below ground, causing instabilities within the IC. To be effective, the diode selected should have a forward drop of less than 0.3 V at 200 mA. Most 1- to 3-A Schottky diodes exhibit these traits above room temperature. Placing the diode as physically close to the PWM as possible enhances circuit performance. Implementation of the complete drive scheme is shown in Figure 7-7 through Figure 7-9. Transformer-driven circuits also require the use of the Schottky diodes to prevent a similar set of circumstances from occurring on the PWM output. The ringing below ground is greatly enhanced by the transformer leakage inductance and parasitic capacitance, in addition to the magnetizing inductance and FET gate capacitance. Circuit implementation is similar to the previous example.

Figure 7-7 through Figure 7-9 show suggested circuits for driving MOSFETs and bipolar transistors with the UC1843B-SP output. The simple circuit of Figure 7-7 can be used when the control IC is not electrically isolated from the MOSFET turnon and turnoff to ±1 A. It also provides damping for a parasitic tank circuit formed by the FET input capacitance and series wiring inductance. Schottky diode, D1, prevents the output of the IC from going far below ground during turnoff.

Figure 7-8 shows an isolated MOSFET drive circuit which is appropriate when the drive signal must be level shifted or transmitted across an isolation boundary. Bipolar transistors can be driven efficiently with the circuit of Figure 7-9. Resistors R1 and R2 fix the on-state base current while capacitor Cl provides a negative base current pulse to remove stored charge at turnoff.

Because the UC1843B-SP series has only a single output, an interface circuit is needed to control push-pull, half-bridge, or full-bridge topologies. The UC1706 dual output driver with internal toggle flip-flop performs this function. Section 8.2 shows a typical application for these two ICs. Increased drive capability for driving numerous FETs in parallel, or other loads can be accomplished using one of the UC1705/7-SP driver ICs.

GUID-20B31050-DC1C-4AFF-B228-B186A4C6D3BE-low.gifFigure 7-7 Direct MOSFET Drive
GUID-1BF0887C-EEBA-4B56-A962-0377E3EC45A9-low.gifFigure 7-8 Isolated MOSFET Drive
GUID-6B4DAD70-386A-4BA6-8572-12D739EEEBD8-low.gifFigure 7-9 Bipolar Drive With Negative Turnoff Bias