SGLS384A May   2008  – November 2022 UC2843A-Q1

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Electrical Characteristics
    5. 6.5 Thermal Information
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Pulse-by-Pulse Current Limiting
      2. 7.3.2 Current Sense Circuit
      3. 7.3.3 Error Amplifier Configuration
      4. 7.3.4 Undervoltage Lockout
      5. 7.3.5 Oscillator
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Undervoltage Lockout (UVLO) Start-Up
      3. 7.4.3 UVLO Turnoff Mode
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Custom Design With WEBENCH® Tools
      2. 11.1.2 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Support Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Undervoltage Lockout

The UC2843A-Q1 device features undervoltage lockout protection circuits for controlled operation during power-up and power-down sequences. Undervoltage lockout thresholds for the UC2843A-Q1 device is optimized for two groups of applications: off-line power supplies and DC-DC converters. The UC2843A-Q1 controller has a much narrower VCCON to VCCOFF hysteresis and may be used in DC to DC applications where the input is considered regulated.

During UVLO the device draws typically 0.3 mA of supply current. The low VCC current of the UC2843A-Q1 results in lower power drawn from the line. The reduced start-up current is of particular concern in off-line supplies where the devive is powered-up from the high-voltage DC rail, then bootstrapped to an auxiliary winding on the main transformer. Power is then dissipated in the start-up resistor which is sized by the devive’s start-up current. Lowering this by 50% in the UC2843A-Q1 reduces the resistors power loss by the same percentage. Once crossing the turnon threshold the device supply current increases typically to about 11 mA, During undervoltage lockout, the UC2843A-Q1 device prevent the power MOSFET from parasitically turning on due to the Miller effect at power-up. This improved design to the lower totem-pole transistor’s operation during undervoltage lockout allows the devives to sink higher currents, up to 10 mA, at saturation voltages as low as 0.7 V, compared to the UCx84x devices which would only sink up to 0.2 mA under the same conditions.

GUID-F2BE17BD-DDAA-4831-8867-4E342EC69F49-low.gifFigure 7-3 Undervoltage Lockout