SLUSCV8B April   2017  – November 2026 UCC20225

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety-Related Certifications
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics
    10. 5.10 Switching Characteristics
    11. 5.11 Thermal Derating Curves
    12. 5.12 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Propagation Delay and Pulse Duration Distortion
    2. 6.2 Rising and Falling Time
    3. 6.3 PWM Input and Disable Response Time
    4. 6.4 Programable Dead Time
    5. 6.5 Power-up UVLO Delay to OUTPUT
    6. 6.6 CMTI Testing
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VDD, VCCI, and Undervoltage Lockout (UVLO)
      2. 7.3.2 Input and Output Logic Table
      3. 7.3.3 Input Stage
      4. 7.3.4 Output Stage
      5. 7.3.5 Diode Structure in UCC20225
    4. 7.4 Device Functional Modes
      1. 7.4.1 Disable Pin
      2. 7.4.2 Programmable Dead Time (DT) Pin
        1. 7.4.2.1 Tying the DT Pin to VCC
        2. 7.4.2.2 DT Pin Left Open or Connected to a Programming Resistor Between DT and GND Pins
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Designing PWM Input Filter
        2. 8.2.2.2 Select External Bootstrap Diode and its Series Resistor
        3. 8.2.2.3 Gate Driver Output Resistor
        4. 8.2.2.4 Estimate Gate Driver Power Loss
        5. 8.2.2.5 Estimating Junction Temperature
        6. 8.2.2.6 Selecting VCCI, VDDA/B Capacitor
          1. 8.2.2.6.1 Selecting a VCCI Capacitor
          2. 8.2.2.6.2 Selecting a VDDA (Bootstrap) Capacitor
          3. 8.2.2.6.3 Select a VDDB Capacitor
        7. 8.2.2.7 Dead Time Setting Guidelines
        8. 8.2.2.8 Application Circuits with Output Stage Negative Bias
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Component Placement
        2. 8.4.1.2 Grounding Considerations
        3. 8.4.1.3 High-Voltage Considerations
        4. 8.4.1.4 Thermal Considerations
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Certifications
    4. 9.4 Receiving Notification of Documentation Updates
    5. 9.5 Support Resources
    6. 9.6 Trademarks
    7. 9.7 Electrostatic Discharge Caution
    8. 9.8 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

UCC20225 NPL Package13-Pin LGATop ViewFigure 4-1 NPL Package13-Pin LGATop View
Table 4-1 Pin Function
PINTYPE(1)DESCRIPTION
NAMENO.
DISABLE5IDisables both driver outputs if asserted high, enables if set low or left open. This pin is pulled low internally if left open. It is recommended to tie this pin to ground if not used to achieve better noise immunity. Bypass using a ≈1nF low ESR or ESL capacitor close to DIS pin when connecting to a microcontroller with distance.
DT6IProgrammable dead time function.

Tying DT to VCCI disables the DT function with dead time ≈ 0ns. Leaving DT open sets the dead time to <15ns. Placing a resistor (RDT) between DT and GND adjusts dead time according to: DT (in ns) = 10 × RDT (in kΩ). It is recommended to parallel a ceramic capacitor, 2.2nF or above, close to DT pin to achieve better noise immunity.

GND1GPrimary-side ground reference. All signals in the primary side are referenced to this ground.
NC3–No internal connection.
OUTA12OOutput of driver A. Connect to the gate of the A channel FET or IGBT. Output A is in phase with PWM input with a propagation delay
OUTB9OOutput of driver B. Connect to the gate of the B channel FET or IGBT. Output B is always complementary to output A with a programmed dead time.
PWM2IPWM input has a TTL/CMOS compatible input threshold. This pin is pulled low internally if left open.
VCCI4PPrimary-side supply voltage. Locally decoupled to GND using a low ESR/ESL capacitor located as close to the device as possible.
VCCI7PPrimary-side supply voltage. This pin is internally shorted to pin 4.
VDDA13PSecondary-side power for driver A. Locally decoupled to VSSA using a low ESR/ESL capacitor located as close to the device as possible.
VDDB10PSecondary-side power for driver B. Locally decoupled to VSSB using a low ESR/ESL capacitor located as close to the device as possible.
VSSA11GGround for secondary-side driver A. Ground reference for secondary side A channel.
VSSB8GGround for secondary-side driver B. Ground reference for secondary side B channel.
(1) P = Power, G = Ground, I = Input, O = Output