SLUSCX6C February   2018  – November 2024 UCC21222

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety Limiting Values
    8. 5.8  Electrical Characteristics
    9. 5.9  Switching Characteristics
    10. 5.10 Insulation Characteristics Curves
    11. 5.11 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Propagation Delay and Pulse Width Distortion
    2. 6.2 Rising and Falling Time
    3. 6.3 Input and Disable Response Time
    4. 6.4 Programmable Dead Time
    5. 6.5 Power-up UVLO Delay to OUTPUT
    6. 6.6 CMTI Testing
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VDD, VCCI, and Undervoltage Lock Out (UVLO)
      2. 7.3.2 Input and Output Logic Table
      3. 7.3.3 Input Stage
      4. 7.3.4 Output Stage
      5. 7.3.5 Diode Structure in the UCC21222
    4. 7.4 Device Functional Modes
      1. 7.4.1 Disable Pin
      2. 7.4.2 Programmable Dead-Time (DT) Pin
        1. 7.4.2.1 Tying the DT Pin to VCC
        2. 7.4.2.2 DT Pin Connected to a Programming Resistor Between DT and GND Pins
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Designing INA/INB Input Filter
        2. 8.2.2.2 Select External Bootstrap Diode and its Series Resistor
        3. 8.2.2.3 Gate Driver Output Resistor
        4. 8.2.2.4 Gate to Source Resistor Selection
        5. 8.2.2.5 Estimate Gate Driver Power Loss
        6. 8.2.2.6 Estimating Junction Temperature
        7. 8.2.2.7 Selecting VCCI, VDDA/B Capacitor
          1. 8.2.2.7.1 Selecting a VCCI Capacitor
          2. 8.2.2.7.2 Selecting a VDDA (Bootstrap) Capacitor
          3. 8.2.2.7.3 Select a VDDB Capacitor
        8. 8.2.2.8 Dead Time Setting Guidelines
        9. 8.2.2.9 Application Circuits with Output Stage Negative Bias
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Certifications
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Support Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

12 Revision History

Changes from Revision B (February 2024) to Revision C (November 2024)

  • Updated Features section to reflect device characteristicsGo
  • Added junction temperature rangeGo
  • Changed CMTI from greater than 100V/ns to greater than 125V/nsGo
  • Changed maximum VDD output drive supply from 18V to 25VGo
  • Changed typical propagation delay from 28ns to 33nsGo
  • Deleted bullet on maximum delay matchingGo
  • Changed maximum pulse-width distortion from 5.5ns to 5nsGo
  • Deleted bullet on minimum pulse widthGo
  • Added maximum VDD power-up delay of 10usGo
  • Deleted bullets on isolation barrier life and surge immunityGo
  • Updated certification to the latest standardsGo
  • Updated applications sectionGo
  • Updated description section to reflect device characteristicsGo
  • Changed CMTI from greater than 100V/ns to greater than 125V/nsGo
  • Deleted sentence on negative voltage handlingGo
  • Changed Functional Block Diagram to Typical Application SchematicGo
  • Changed DIS pin description; leaving DIS pin open would disable the device, and the pin is internally pulled high instead of lowGo
  • Deleted DT pin recommended capacitor size of 2.2nF or greater. Changed DT pin equationGo
  • Added INA and INB RC filter recommendationGo
  • Changed all -0.5V minimum to -0.3V to keep consistent with newly released datasheetsGo
  • Changed VDDA-VSSA and VDDB-VSSB absmax from 20V to 30VGo
  • Changed all absolute maximum value from supply+0.5V to supply+0.3V to keep consistent with newly released datasheetsGo
  • Changed input signal trasient voltage from -2V to -5V and changed test condition from 200ns to 50nsGo
  • Added D package channel to channel isolation voltageGo
  • Updated ESD spec from HBM = ±4000 and CDM = ±1500 to HBM = ±2000 and CDM = ±1000 to match ESD industry standardsGo
  • Changed VDDA-VSSA and VDDB-VSSB recommended max from 18V to 25VGo
  • Deleted ambient temperature specGo
  • Changed junction temperature max from 130°C to 150°CGo
  • Updated thermal values from RθJA = 68.5°C/W, RθJC(top) = 30.5°C/W, RθJB = 22.8°C/W, ψJT = 17.1°C/W, ψJB = 22.5°C/W to RθJA = 80.2°C/W, RθJC(top) = 36.6°C/W, RθJB = 45°C/W, ψJT = 28°C/W, ψJB = 44.3°C/WGo
  • Updated values from PD = 1825mW, PDI = 15mW, PDA/PDB = 905mW to PD = 950mW, PDI = 50mW, PDA/PDB = 450mW. Changed test conditionsGo
  • Updated DIN EN IEC to the latest standard, updated insulation voltage valuesGo
  • Changed barrier capacitance from 0.5pF to ~1.2pFGo
  • Deleted safety-related certifications section, certification ongoingGo
  • Changed IS testing condition. Changed IS value from 75mA (with VDDA/B=12V) to 50mA (with VDDA/B=15V) and 30mA (with VDDA/B=25V).Go
  • Updated safety-limiting values from PS = 15mW/905mW/905mW/1825mW to PS = 50mW/750mW/750mW/1550mWGo
  • Updated IVCCI quiescent current spec Typ value from 1.5mA to 1.4mAGo
  • Added more test conditions for IVCC and IVDDGo
  • Updated IVCCI operating current Typ value from 2.5mA to 2.7mA and added Max value 3.2mAGo
  • Updated IVDDA/IVDDB quiescent current spec Typ from 1.0mA to 1.2mA and Max value from 1.8mA to 2.0mAGo
  • Updated IVDDA/IVDDB operating current Typ value from 2.5mA to 2.7mA and added Max value 4.4mA. Deleted Cload from test condition.Go
  • Changed VCCI power-up delay from Typ = 40us to Min = 18us, Max = 80usGo
  • Added VCC UVLO OFF delay and deglitch specsGo
  • Updated values from Rising threshold Min = 8V, Typ = 8.5V, Max = 9V to Min = 7.7V, Typ = 8.5V, Max = 8.9VGo
  • Updated values from Falling threshold Min = 7.5V, Typ = 8V, Max = 8.5V to Min = 7.2V, Typ = 7.9V, Max = 8.4VGo
  • Updated 8-V UVLO hysteresis typ = 0.5V to 0.6VGo
  • Deleted VDD power up delay Typ 22us and added Max value of 10usGo
  • Added VDD UVLO OFF delay and deglitch specsGo
  • Updated Input high threshold Typ = 1.8V, Max = 2V to Typ = 2V, Max = 2.3V. Deleted Min specGo
  • Deleted Input low threshold voltage Max specGo
  • Updated Input threshold hysteresis Typ = 0.8V to Typ = 1VGo
  • Added spec INx Pin Pull Down ResistanceGo
  • Updated peak current test condition to 0.22uF load capacitance. Changed peak output source current directionGo
  • Updated output resistance test condition from ±10mA to ±0.05AGo
  • Deleted output voltage at high/low state specsGo
  • Updated active pull-down Typ = 1.75V, Max = 2.1V to Typ = 1.6V, Max = 2VGo
  • Updated DT pin specs, deleted dead time matchingGo
  • Changed output rise time Typ from 5ns to 8ns. Deleted Max valueGo
  • Changed output fall time Typ from 6ns to 8ns. Deleted Max valueGo
  • Changed propagation delay TPDHL and TPDLH from Typ=28ns, Max = 40ns to Min = 26ns, Typ = 33ns, Max = 45nsGo
  • Changed minimum pulse width from Typ = 10ns, Max = 20ns to Min = 4ns, Typ = 12ns, Max = 30nsGo
  • Changed propagation delay matching from Max = 5ns to Max = 6.5ns from TJ = -40C to -10C and Max = 5ns from TJ = -10C to 150CGo
  • Changed pulse width distortion max from 5.5ns to 5nsGo
  • Updated CMTI from Min = 100V/ns to 125V/nsGo
  • Updated thermal curves to match updated characteristicsGo
  • Updated typical char plots to show device characteristics Go
  • Deleted mininum pulses in parameter measurement informationGo
  • Changed DT formula. Deleted recommended DT decoupling capacitor size of 2.2nF or greaterGo
  • Updated UVLO delay to match new specsGo
  • Updated functional block diagram to reflect device characteristicsGo
  • Changed logic table; leaving DIS pin open disables the driverGo
  • Updated input stage section to match new specsGo
  • Added paragraph on minimum pulse width to Output Stage sectionGo
  • Updated ESD structure diagram to reflect device characteristicsGo
  • Changed dead time equation, deleted recommendation on 2.2nF or greater DT capacitorGo
  • Changed typical application schematic to remove DT capacitorGo
  • Updated applications sections to match the latest specsGo
  • Added Dead Time Setting Guidelines sectionGo
  • Changed maximum VDDA/VDDB from 18V to 25VGo
  • Deleted DT capacitor size recommendation of ≥ 2.2 nFGo
  • Updated layout guidelinesGo

Changes from Revision A (April 2018) to Revision B (February 2024)

  • Changed CTI and Material Group values in insulation specifications and added table noteGo