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Product details

Parameters

Number of channels (#) 2 Isolation rating (Vrms) 3000 Power switch MOSFET, IGBT, GaNFET Peak output current (A) 6 DIN V VDE V 0884-10 transient overvoltage rating (Vpk) 4242 DIN V VDE V 0884-10 working voltage (Vpk) 990 Output VCC/VDD (Max) (V) 18 Output VCC/VDD (Min) (V) 9.2 Input VCC (Min) (V) 3 Input VCC (Max) (V) 5.5 Prop delay (ns) 28 Operating temperature range (C) -40 to 125 Undervoltage lockout (Typ) 8 open-in-new Find other Isolated gate drivers

Package | Pins | Size

SOIC (D) 16 59 mm² 9.9 x 6 open-in-new Find other Isolated gate drivers

Features

  • Resistor-Programmable Dead Time
  • Universal: Dual Low-Side, Dual High-Side or Half-Bridge Driver
  • 4-A Peak Source, 6-A Peak Sink Output
  • 3-V to 5.5-V Input VCCI Range
  • Up to 18-V VDD Output Drive Supply
    • 8-V VDD UVLO
  • Switching Parameters:
    • 28-ns Typical Propagation Delay
    • 10-ns Minimum Pulse Width
    • 5-ns Maximum Delay Matching
    • 5.5-ns Maximum Pulse-Width Distortion
  • TTL and CMOS Compatible Inputs
  • Integrated Deglitch Filter
  • I/Os withstand –2-V for 200 ns
  • Common-Mode Transient Immunity (CMTI) Greater than 100-V/ns
  • Isolation Barrier Life >40 Years
  • Surge Immunity up to 7800-VPK
  • Narrow Body SOIC-16 (D) Package
  • Safety-Related Certifications (Planned):
    • 4242-VPK Isolation per DIN V VDE V 0884-11:2017-01 and DIN EN 61010-1
    • 3000-VRMS Isolation for 1 Minute per UL 1577
    • CSA Certification per IEC 60950-1, IEC 62368-1 and IEC 61010-1 End Equipment Standards
    • CQC Certification per GB4943.1-2011
  • Create a Custom Design Using the UCC21222 With the WEBENCH® Power Designer
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Description

The UCC21222 device is an isolated dual channel gate driver with programmable dead time. It is designed with 4-A peak-source and 6-A peak-sink current to drive power MOSFET, IGBT, and GaN transistors.

The UCC21222 device can be configured as two low-side drivers, two high-side drivers, or a half-bridge driver. 5ns delay matching performance allows two outputs to be paralleled, doubling the drive strength for heavy load conditions without risk of internal shoot-through.

The input side is isolated from the two output drivers by a 3.0-kVRMS isolation barrier, with a minimum of 100-V/ns common-mode transient immunity (CMTI).

Resistor programmable dead time gives the capability to adjust dead time for system constraints to improve efficiency and prevent output overlap. Other protection features include: Disable feature to shut down both outputs simultaneously when DIS is set high, integrated deglitch filter that rejects input transients shorter than 5-ns, and negative voltage handling for up to -2-V spikes for 200-ns on input and output pins. All supplies have UVLO protection.

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Technical documentation

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Type Title Date
* Data sheet UCC21222 4-A, 6-A, 3.0-kVRMS Isolated Dual-Channel Gate Driver with Dead Time datasheet (Rev. A) Apr. 13, 2018
Certificate VDE Certificate for Basic Isolation for DIN VDE V 0884-11:2017-01 (Rev. S) Aug. 03, 2021
Test report Peak Efficiency at 99%, 585-W High-Voltage Buck Reference Design Apr. 24, 2020
Application note External Gate Resistor Selection Guide (Rev. A) Feb. 28, 2020
Application note Understanding Peak IOH and IOL Currents (Rev. A) Feb. 28, 2020
Certificate UL Certification E181974 Vol 4. Sec 9 (Rev. A) Jul. 22, 2019
User guide Gate Drive Voltage vs. Efficiency Apr. 25, 2019
Application note How to Drive High Voltage GaN FETs with UCC21220A Mar. 06, 2019
White paper Impact of an isolated gate driver (Rev. A) Feb. 20, 2019
Technical article How to achieve higher system robustness in DC drives, part 3: minimum input pulse Sep. 19, 2018
Application note Common Mode Transient Immunity (CMTI) for UCC2122x Isolated Gate Drivers Jul. 19, 2018
White paper Demystifying high-voltage power electronics for solar inverters Jun. 06, 2018
Application note Solar Inverter Layout Considerations for UCC21220 Jun. 06, 2018
Technical article How to achieve higher system robustness in DC drives, part 2: interlock and deadtime May 30, 2018
Technical article Boosting efficiency for your solar inverter designs May 24, 2018
Technical article How to achieve higher system robustness in DC drives, part 1: negative voltage Apr. 17, 2018

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
document-generic User guide
49
Description
UCC21220EVM-009 is designed for evaluating UCC21220, which is a 3.0-kVRMS Isolated Dual-Channel Gate Driver with 4.0-A source and 6.0-A sink peak current capability. This EVM could be served to evaluate the driver IC against its datsheet. The EVM can also be used as Driver IC component selection (...)
Features
  • High performance driver with input and output interface.
  • Ability to test most data sheet parameters
  • Ability to compare performance of various drivers with compatible pinout

Design tools & simulation

SIMULATION MODEL Download
SLUM622.ZIP (57 KB) - PSpice Model
SIMULATION MODEL Download
SLUM623.ZIP (3 KB) - PSpice Model
SIMULATION TOOL Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
CALCULATION TOOL Download
SLURAZ5.ZIP (609 KB)

Reference designs

REFERENCE DESIGNS Download
4-kW single-phase totem pole PFC reference design with C2000 and GaN
TIDA-010203 — This reference design is a 4-kW CCM totem-pole PFC with F280049/F280025 control card and LMG342x EVM board. This design demos a robust PFC solution, which avoids isolated current sense by putting the controller's ground in the middle of a MOSFET leg. Benefitting from non-isolation, AC current sense (...)
document-generic Schematic
REFERENCE DESIGNS Download
54-Vdc input, 12-V 4-A output half-bridge reference design
PMP40500 — This 12-V, 42-A output half-bridge reference design is for bus converters in wired networking campus and branch switches. The design features high efficiency and various fault protections (over-current, short-circuit). The guide provides a efficiency comparison using 3kVrms basic and functional (...)
document-generic Schematic

CAD/CAE symbols

Package Pins Download
SOIC (D) 16 View options

Ordering & quality

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  • Ongoing reliability monitoring

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