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UCC21222

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3kVrms, 4A/6A dual-channel isolated gate driver w/ disable pin, programmable deadtime, 8V UVLO

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Data sheet

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UCC21330 ACTIVE 3kVrms, 4A/6A dual-channel isolated gate driver w/ disable logic, programmable deadtime, 8V UVLO Improved CMTI, faster VDD startup

UCC21222

ACTIVE
Data sheet Order now

Product details

Number of channels 2 Isolation rating Basic Power switch GaNFET, IGBT, MOSFET Withstand isolation voltage (VISO) (Vrms) 3000 Working isolation voltage (VIOWM) (Vrms) 990 Transient isolation voltage (VIOTM) (VPK) 4242 Peak output current (A) 6 Peak output current (source) (typ) (A) 4 Peak output current (sink) (typ) (A) 6 Features Disable, Programmable dead time Output VCC/VDD (min) (V) 9.2 Output VCC/VDD (max) (V) 18 Input supply voltage (min) (V) 3 Input supply voltage (max) (V) 5.5 Propagation delay time (µs) 0.028 Input threshold CMOS, TTL Operating temperature range (°C) -40 to 125 Rating Catalog Rise time (ns) 5 Fall time (ns) 6 Undervoltage lockout (typ) (V) 8
Number of channels 2 Isolation rating Basic Power switch GaNFET, IGBT, MOSFET Withstand isolation voltage (VISO) (Vrms) 3000 Working isolation voltage (VIOWM) (Vrms) 990 Transient isolation voltage (VIOTM) (VPK) 4242 Peak output current (A) 6 Peak output current (source) (typ) (A) 4 Peak output current (sink) (typ) (A) 6 Features Disable, Programmable dead time Output VCC/VDD (min) (V) 9.2 Output VCC/VDD (max) (V) 18 Input supply voltage (min) (V) 3 Input supply voltage (max) (V) 5.5 Propagation delay time (µs) 0.028 Input threshold CMOS, TTL Operating temperature range (°C) -40 to 125 Rating Catalog Rise time (ns) 5 Fall time (ns) 6 Undervoltage lockout (typ) (V) 8
SOIC (D) 16 59.4 mm² 9.9 x 6

  • Universal: dual low-side, dual high-side or halfbridge driver

  • Junction temperature range –40 to +150°C
  • Up to 4A peak source and 6A peak sink output
  • Common-mode transient immunity (CMTI) greater than 125V/ns
  • Up to 25V VDD output drive supply
    • 8V, VDD UVLO options
  • Switching parameters:
    • 33ns typical propagation delay
    • 5ns maximum pulse-width distortion
    • 10µs maximum VDD power-up delay
  • UVLO protection for all power supplies
  • Fast disable for power sequencing
  • Safety-related certifications (planned):
    • 4242VPK isolation per DIN EN IEC 60747-17 (VDE 0884-17)
    • 3000VRMS isolation for 1 minute per UL 1577
    • CQC Certification per GB4943.1-2022

  • Universal: dual low-side, dual high-side or halfbridge driver

  • Junction temperature range –40 to +150°C
  • Up to 4A peak source and 6A peak sink output
  • Common-mode transient immunity (CMTI) greater than 125V/ns
  • Up to 25V VDD output drive supply
    • 8V, VDD UVLO options
  • Switching parameters:
    • 33ns typical propagation delay
    • 5ns maximum pulse-width distortion
    • 10µs maximum VDD power-up delay
  • UVLO protection for all power supplies
  • Fast disable for power sequencing
  • Safety-related certifications (planned):
    • 4242VPK isolation per DIN EN IEC 60747-17 (VDE 0884-17)
    • 3000VRMS isolation for 1 minute per UL 1577
    • CQC Certification per GB4943.1-2022

The UCC21222 is an isolated dual channel gate driver family with programmable dead time and wide temperature range. It is designed with 4A peak-source and 6A peak-sink current to drive power MOSFET, SiC, GaN, and IGBT transistors.

The UCC21222 can be configured as two low-side drivers, two high-side drivers, or a half-bridge driver. The input side is isolated from the two output drivers by a 3kVRMS isolation barrier, with a minimum of 125V/ns common-mode transient immunity (CMTI).

Protection features include: resistor programmable dead time, disable feature to shut down both outputs simultaneously, and integrated de-glitch filter that rejects input transients shorter than 5ns. All supplies have UVLO protection.

With all these advanced features, the UCC21222 device enables high efficiency, high power density, and robustness in a wide variety of power applications.

The UCC21222 is an isolated dual channel gate driver family with programmable dead time and wide temperature range. It is designed with 4A peak-source and 6A peak-sink current to drive power MOSFET, SiC, GaN, and IGBT transistors.

The UCC21222 can be configured as two low-side drivers, two high-side drivers, or a half-bridge driver. The input side is isolated from the two output drivers by a 3kVRMS isolation barrier, with a minimum of 125V/ns common-mode transient immunity (CMTI).

Protection features include: resistor programmable dead time, disable feature to shut down both outputs simultaneously, and integrated de-glitch filter that rejects input transients shorter than 5ns. All supplies have UVLO protection.

With all these advanced features, the UCC21222 device enables high efficiency, high power density, and robustness in a wide variety of power applications.
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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet UCC21222 4A, 6A, 3kVRMS Isolated Dual-Channel Gate Driver datasheet (Rev. C) PDF | HTML 11 Nov 2024
Certificate VDE Certificate for Basic Isolation for DIN EN IEC 60747-17 (Rev. Z) 29 May 2026
Certificate UCC21220 CQC Certificate of Product Certification 16 Aug 2023
Application brief The Use and Benefits of Ferrite Beads in Gate Drive Circuits PDF | HTML 16 Dec 2021
Certificate FPPT2 - Nonoptical Isolating Devices UL 1577 Certificate of Compliance 26 Oct 2021
Test report Peak Efficiency at 99%, 585-W High-Voltage Buck Reference Design 24 Apr 2020
Application brief External Gate Resistor Selection Guide (Rev. A) 28 Feb 2020
Application brief Understanding Peak IOH and IOL Currents (Rev. A) 28 Feb 2020
Certificate UL Certification E181974 Vol 4. Sec 9 (Rev. A) 22 Jul 2019
User guide Gate Drive Voltage vs. Efficiency 25 Apr 2019
Application brief How to Drive High Voltage GaN FETs with UCC21220A 06 Mar 2019
White paper Impact of an isolated gate driver (Rev. A) 20 Feb 2019
Application note Common Mode Transient Immunity (CMTI) for UCC2122x Isolated Gate Drivers 19 Jul 2018
White paper Demystifying high-voltage power electronics for solar inverters 06 Jun 2018
Application note Solar Inverter Layout Considerations for UCC21220 06 Jun 2018
Technical article Boosting efficiency for your solar inverter designs PDF | HTML 24 May 2018

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