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UCC21222

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3.0kVrms 4A/6A dual-channel isolated gate driver with disable pin, programmable deadtime & 8V UVLO

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Data sheet

UCC21222

ACTIVE
Data sheet Order now

Product details

Number of channels 2 Withstand isolation voltage (VISO) (Vrms) 3000 Power switch GaNFET, IGBT, MOSFET Peak output current (A) 6 Features Disable, Programmable dead time Output VCC/VDD (max) (V) 18 Output VCC/VDD (min) (V) 9.2 Input VCC (min) (V) 3 Input VCC (max) (V) 5.5 Propagation delay time (µs) 0.028 Input threshold CMOS, TTL Operating temperature range (°C) -40 to 125 Rating Catalog Bus voltage (max) (V) 990 Fall time (ns) 6 Undervoltage lockout (typ) (V) 8
Number of channels 2 Withstand isolation voltage (VISO) (Vrms) 3000 Power switch GaNFET, IGBT, MOSFET Peak output current (A) 6 Features Disable, Programmable dead time Output VCC/VDD (max) (V) 18 Output VCC/VDD (min) (V) 9.2 Input VCC (min) (V) 3 Input VCC (max) (V) 5.5 Propagation delay time (µs) 0.028 Input threshold CMOS, TTL Operating temperature range (°C) -40 to 125 Rating Catalog Bus voltage (max) (V) 990 Fall time (ns) 6 Undervoltage lockout (typ) (V) 8
SOIC (D) 16 59.4 mm² 9.9 x 6
  • Resistor-Programmable Dead Time
  • Universal: Dual Low-Side, Dual High-Side or Half-Bridge Driver
  • 4-A Peak Source, 6-A Peak Sink Output
  • 3-V to 5.5-V Input VCCI Range
  • Up to 18-V VDD Output Drive Supply
    • 8-V VDD UVLO
  • Switching Parameters:
    • 28-ns Typical Propagation Delay
    • 10-ns Minimum Pulse Width
    • 5-ns Maximum Delay Matching
    • 5.5-ns Maximum Pulse-Width Distortion
  • TTL and CMOS Compatible Inputs
  • Integrated Deglitch Filter
  • I/Os withstand –2-V for 200 ns
  • Common-Mode Transient Immunity (CMTI) Greater than 100-V/ns
  • Isolation Barrier Life >40 Years
  • Surge Immunity up to 7800-VPK
  • Narrow Body SOIC-16 (D) Package
  • Safety-Related Certifications (Planned):
    • 4242-VPK Isolation per DIN V VDE V 0884-11:2017-01 and DIN EN 61010-1
    • 3000-VRMS Isolation for 1 Minute per UL 1577
    • CSA Certification per IEC 60950-1, IEC 62368-1 and IEC 61010-1 End Equipment Standards
    • CQC Certification per GB4943.1-2011
  • Create a Custom Design Using the UCC21222 With the WEBENCH® Power Designer
  • Resistor-Programmable Dead Time
  • Universal: Dual Low-Side, Dual High-Side or Half-Bridge Driver
  • 4-A Peak Source, 6-A Peak Sink Output
  • 3-V to 5.5-V Input VCCI Range
  • Up to 18-V VDD Output Drive Supply
    • 8-V VDD UVLO
  • Switching Parameters:
    • 28-ns Typical Propagation Delay
    • 10-ns Minimum Pulse Width
    • 5-ns Maximum Delay Matching
    • 5.5-ns Maximum Pulse-Width Distortion
  • TTL and CMOS Compatible Inputs
  • Integrated Deglitch Filter
  • I/Os withstand –2-V for 200 ns
  • Common-Mode Transient Immunity (CMTI) Greater than 100-V/ns
  • Isolation Barrier Life >40 Years
  • Surge Immunity up to 7800-VPK
  • Narrow Body SOIC-16 (D) Package
  • Safety-Related Certifications (Planned):
    • 4242-VPK Isolation per DIN V VDE V 0884-11:2017-01 and DIN EN 61010-1
    • 3000-VRMS Isolation for 1 Minute per UL 1577
    • CSA Certification per IEC 60950-1, IEC 62368-1 and IEC 61010-1 End Equipment Standards
    • CQC Certification per GB4943.1-2011
  • Create a Custom Design Using the UCC21222 With the WEBENCH® Power Designer

The UCC21222 device is an isolated dual channel gate driver with programmable dead time. It is designed with 4-A peak-source and 6-A peak-sink current to drive power MOSFET, IGBT, and GaN transistors.

The UCC21222 device can be configured as two low-side drivers, two high-side drivers, or a half-bridge driver. 5ns delay matching performance allows two outputs to be paralleled, doubling the drive strength for heavy load conditions without risk of internal shoot-through.

The input side is isolated from the two output drivers by a 3.0-kVRMS isolation barrier, with a minimum of 100-V/ns common-mode transient immunity (CMTI).

Resistor programmable dead time gives the capability to adjust dead time for system constraints to improve efficiency and prevent output overlap. Other protection features include: Disable feature to shut down both outputs simultaneously when DIS is set high, integrated deglitch filter that rejects input transients shorter than 5-ns, and negative voltage handling for up to -2-V spikes for 200-ns on input and output pins. All supplies have UVLO protection.

The UCC21222 device is an isolated dual channel gate driver with programmable dead time. It is designed with 4-A peak-source and 6-A peak-sink current to drive power MOSFET, IGBT, and GaN transistors.

The UCC21222 device can be configured as two low-side drivers, two high-side drivers, or a half-bridge driver. 5ns delay matching performance allows two outputs to be paralleled, doubling the drive strength for heavy load conditions without risk of internal shoot-through.

The input side is isolated from the two output drivers by a 3.0-kVRMS isolation barrier, with a minimum of 100-V/ns common-mode transient immunity (CMTI).

Resistor programmable dead time gives the capability to adjust dead time for system constraints to improve efficiency and prevent output overlap. Other protection features include: Disable feature to shut down both outputs simultaneously when DIS is set high, integrated deglitch filter that rejects input transients shorter than 5-ns, and negative voltage handling for up to -2-V spikes for 200-ns on input and output pins. All supplies have UVLO protection.
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Technical documentation

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Type Title Date
* Data sheet UCC21222 4-A, 6-A, 3.0-kVRMS Isolated Dual-Channel Gate Driver with Dead Time datasheet (Rev. A) PDF | HTML 13 Apr 2018
Certificate VDE Certificate for Basic Isolation for DIN EN IEC 60747-17 (Rev. U) 07 Feb 2023
More literature The Use and Benefits of Ferrite Beads in Gate Drive Circuits PDF | HTML 16 Dec 2021
Certificate FPPT2 - Nonoptical Isolating Devices UL 1577 Certificate of Compliance 26 Oct 2021
Test report Peak Efficiency at 99%, 585-W High-Voltage Buck Reference Design 24 Apr 2020
More literature External Gate Resistor Selection Guide (Rev. A) 28 Feb 2020
More literature Understanding Peak IOH and IOL Currents (Rev. A) 28 Feb 2020
Certificate UL Certification E181974 Vol 4. Sec 9 (Rev. A) 22 Jul 2019
User guide Gate Drive Voltage vs. Efficiency 25 Apr 2019
More literature How to Drive High Voltage GaN FETs with UCC21220A 06 Mar 2019
More literature Impact of an isolated gate driver (Rev. A) 20 Feb 2019
Technical article How to achieve higher system robustness in DC drives, part 3: minimum input pulse 19 Sep 2018
More literature Common Mode Transient Immunity (CMTI) for UCC2122x Isolated Gate Drivers 19 Jul 2018
More literature Demystifying high-voltage power electronics for solar inverters 06 Jun 2018
More literature Solar Inverter Layout Considerations for UCC21220 06 Jun 2018
Technical article How to achieve higher system robustness in DC drives, part 2: interlock and deadtime 30 May 2018
Technical article Boosting efficiency for your solar inverter designs 24 May 2018
Technical article How to achieve higher system robustness in DC drives, part 1: negative voltage 17 Apr 2018

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

UCC21220EVM-009 — UCC21220 4-A, 6-A 3.0-kVRMS Isolated Dual-Channel Gate Driver Evaluation Module

UCC21220EVM-009 is designed for evaluating UCC21220, which is a 3.0-kVRMS Isolated Dual-Channel Gate Driver with 4.0-A source and 6.0-A sink peak current capability. This EVM could be served to evaluate the driver IC against its datsheet. The EVM can also be used as Driver IC component selection (...)
User guide: PDF
Not available on TI.com
Simulation model

UCC21222-Q1 PSpice Transient Model

SLUM622.ZIP (57 KB) - PSpice Model
Download
Simulation model

UCC21222-Q1 Unencrypted PSpice Transient Model

SLUM623.ZIP (3 KB) - PSpice Model
Download
Calculation tool

UCC21520 Bootstrap Calculator 1.0

SLURAZ5.ZIP (609 KB)
Download
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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Reference designs

PMP41043 — 1.6-kW reference design with CCM totem pole PFC and current-mode LLC realized by C2000 and GaN

This reference design demonstrates a hybrid hysteresis control (HHC) method, a current mode control method on half-bridge LLC stage with a C2000 F28004x microcontroller. The hardware is based on TIDA-010062 which is 1-kW, 80 Plus titanium, GaN CCM totem pole bridgeless PFC and half-bridge LLC (...)
Test report: PDF
Reference designs

TIDA-010203 — 4-kW single-phase totem pole PFC reference design with C2000 and GaN

This reference design is a 4-kW CCM totem-pole PFC with F280049/F280025 control card and LMG342x EVM board. This design demos a robust PFC solution, which avoids isolated current sense by putting the controller's ground in the middle of a MOSFET leg. Benefitting from non-isolation, AC current (...)
Design guide: PDF
Schematic: PDF
Reference designs

PMP41006 — 1-kW reference design with CCM totem pole PFC and current-mode LLC realized by C2000™ and GaN

This reference design demonstrates a hybrid hysteresis control (HHC) method, a kind of current-mode control method on half-bridge LLC stage with a C2000™ F28004x microcontroller. The hardware is based on TIDA-010062, which is 1-kW, 80-Plus titanium, GaN CCM totem pole bridgeless PFC and half-bridge (...)
Test report: PDF
Reference designs

PMP40500 — 54-VDC input, 12-V 42-A output half-bridge reference design

This 12-V, 42-A output half-bridge reference design is for bus converters in wired networking campus and branch switches. The design features high efficiency and various fault protections (over-current and short-circuit). The design provides an efficiency comparison using 3 kVRMS basic and (...)
Test report: PDF
Schematic: PDF
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SOIC (D) 16 View options

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