SLUSDU7 March 2020 UCC21320-Q1
PRODUCTION DATA.
Figure 43 shows a 2-layer PCB layout example with the signals and key components labeled.
Figure 44 and Figure 45 shows top and bottom layer traces and copper.
NOTE
There are no PCB traces or copper between the primary and secondary side, which ensures isolation performance.
PCB traces between the high-side and low-side gate drivers in the output stage are increased to maximize the creepage distance for high-voltage operation, which will also minimize cross-talk between the switching node VSSA (SW), where high dv/dt may exist, and the low-side gate drive due to the parasitic capacitance coupling. Figure 46 shows a 3D view of the bottom side recommended layout, showing the board cutout.
NOTE
The location of the PCB cutout between the primary side and secondary sides, which ensures isolation performance.