SLUSDO2D June   2020  – August 2024 UCC21540-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Limiting Values
    8. 6.8  Electrical Characteristics
    9. 6.9  Switching Characteristics
    10. 6.10 Insulation Characteristics Curves
    11. 6.11 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Minimum Pulses
    2. 7.2 Propagation Delay and Pulse Width Distortion
    3. 7.3 Rising and Falling Time
    4. 7.4 Input and Disable Response Time
    5. 7.5 Programmable Dead Time
    6. 7.6 Power-Up UVLO Delay to OUTPUT
    7. 7.7 CMTI Testing
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)
      2. 8.3.2 Input and Output Logic Table
      3. 8.3.3 Input Stage
      4. 8.3.4 Output Stage
      5. 8.3.5 Diode Structure in the UCC21540-Q1
    4. 8.4 Device Functional Modes
      1. 8.4.1 Disable Pin
      2. 8.4.2 Programmable Dead Time (DT) Pin
        1. 8.4.2.1 DT Pin Tied to VCCI
        2. 8.4.2.2 Connecting a Programming Resistor between DT and GND Pins
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Designing INA/INB Input Filter
        2. 9.2.2.2 Select Dead Time Resistor and Capacitor
        3. 9.2.2.3 Select External Bootstrap Diode and Its Series Resistor
        4. 9.2.2.4 Gate Driver Output Resistor
        5. 9.2.2.5 Gate to Source Resistor Selection
        6. 9.2.2.6 Estimating Gate Driver Power Loss
        7. 9.2.2.7 Estimating Junction Temperature
        8. 9.2.2.8 Selecting VCCI, VDDA/B Capacitor
          1. 9.2.2.8.1 Selecting a VCCI Capacitor
          2. 9.2.2.8.2 Selecting a VDDA (Bootstrap) Capacitor
          3. 9.2.2.8.3 Select a VDDB Capacitor
        9. 9.2.2.9 Application Circuits with Output Stage Negative Bias
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Component Placement Considerations
      2. 11.1.2 Grounding Considerations
      3. 11.1.3 High-Voltage Considerations
      4. 11.1.4 Thermal Considerations
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DWK|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.8 Electrical Characteristics

VVCCI = 3.3 V or 5.0 V, 0.1-µF capacitor from VCCI to GND and 1-µF capacitor from VDDA/B to VSSA/B, VVDDA = VVDDB = 15 V, 1-µF capacitor from VDDA and VDDB to VSSA and VSSB, DT pin tied to VCCI, CL = 0 pF, TJ = –40°C to +150°C unless otherwise noted(1)(2).
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
SUPPLY CURRENTS
IVCCIVCCI quiescent currentVINA = 0 V, VINB = 0 V1.52.0mA
IVDDA, IVDDBVDDA and VDDB quiescent currentVINA = 0 V, VINB = 0 V1.02.5mA
IVCCIVCCI operating currentcurrent per channel (f = 500-kHz, 50% duty cycle)3.03.5mA
IVDDA, IVDDBVDDA and VDDB operating currentcurrent per channel (f = 500 kHz, 50% duty cycle), CL = 100 pF2.54.2mA
VCC SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS
VVCCI_ONUVLO Rising threshold2.552.72.85V
VVCCI_OFFUVLO Falling threshold2.352.52.65V
VVCCI_HYSUVLO Threshold hysteresis0.2V
UCC21540A-Q1 VDD SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS
VVDDA_ON, VVDDB_ON UVLO Rising threshold 5.7 6.0 6.3 V
VVDDA_OFF, VVDDB_OFF UVLO Falling threshold 5.4 5.7 6.0 V
VVDDA_HYS, VVDDB_HYS UVLO Threshold hysteresis 0.3 V
UCC21540-Q1 VDD SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS
VVDDA_ON, VVDDB_ON UVLO Rising threshold 7.7 8.5 8.9 V
VVDDA_OFF, VVDDB_OFF UVLO Falling threshold 7.2 7.9 8.4 V
VVDDA_HYS, VVDDB_HYS UVLO Threshold hysteresis 0.6 V
INA, INB AND DISABLE
VINAH, VINBH, VDISHInput high threshold voltage1.21.82V
VINAL, VINBL, VDISLInput low threshold voltage0.811.2V
VINA_HYS, VINB_HYS, VDIS_HYSInput threshold hysteresis0.8V
OUTPUT
IOA+, IOB+Peak output source currentCVDD = 10 µF, CLOAD = 0.18 µF, f = 1 kHz, bench measurement4A
IOA-, IOB-Peak output sink current6A
ROHA, ROHBOutput resistance at high stateIOUT = –10 mA, ROHA, ROHB do not represent drive pull-up performance. See tRISE in and Section 8.3.4 for details.5Ω
ROLA, ROLBOutput resistance at low stateIOUT = 10 mA0.55Ω
VOHA, VOHBOutput voltage at high stateVVDDA, VVDDB = 15 V, IOUT = –10 mA14.95V
VOLA, VOLBOutput voltage at low stateVVDDA, VVDDB = 15 V, IOUT = 10 mA5.5mV
VOAPDA, VOAPDBDriver output (VOUTA, VOUTB) active pull downVVDDA and VVDDB unpowered, IOUTA, IOUTB = 200 mA 1.62V
DEAD TIME AND OVERLAP PROGRAMMING
Dead time, DTDT pin tied to VCCIOverlap determined by INA, INB-
RDT = 10 kΩ80100120ns
RDT = 20 kΩ160200240
RDT = 50 kΩ400500600
(1) Current direction in the testing conditions are defined to be positive into the pin and negative out of the specified terminal (unless otherwise noted)
(2) Parameters with only a typical value are provided for reference only, and do not constitute part of TI's published device specifications for purposes of TI's product warranty.