Reinforced Isolated Dual-Channel Automotive Gate Driver With 3.3mm Channel-to-Channel Spacing Option
Product details
Parameters
Package | Pins | Size
Features
- Junction temperature range –40°C to 150°C
- Up to 4-A peak source and 6-A peak sink output
- Up to 18-V VDD output drive supply
- CMTI greater than 100 V/ns
- Switching parameters:
- 40-ns maximum propagation delay
- 5-ns maximum delay matching
- 5.5-ns maximum pulse-width distortion
- 35-µs maximum VDD power-up delay
- AEC Q100 qualified with:
- Device temperature grade 1
- Device HBM ESD classification level H2
- Device CDM ESD classification level C6
- Safety-related certifications:
- 8000-VPK reinforced isolation per DIN V VDE V 0884-11:2017-01
- 5700-VRMS isolation for 1 minute per UL 1577
- CQC certification per GB4943.1-2011 (Planned)
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Description
The UCC21540-Q1 device is an isolated dual channel gate driver with programmable dead time and wide temperature range. This device exhibits consistent performance and robustness under extreme temperature conditions. It is designed with 4-A peak-source and 6-A peak-sink current to drive power MOSFET, IGBT, and GaN transistors.
The can be configured as two low-side drivers, two high-side drivers, or a half-bridge driver. The input side is isolated from the two output drivers by a 5.7-kVRMS isolation barrier, with a minimum of 100-V/ns common-mode transient immunity (CMTI).
Protection features include: resistor programmable dead time, disable feature to shut down both outputs simultaneously, integrated de-glitch filter that rejects input transients shorter than 5ns, and negative voltage handling for up to –2V spikes for 200ns on input and output pins. All supplies have UVLO protection.

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The UCC21540-Q1 functional safety manual and functional safety FIT Rate, FMD and Pin FMA report are available. Request now
Technical documentation
Type | Title | Date | |
---|---|---|---|
* | Datasheet | UCC21540-Q1 Reinforced Isolation Dual-Channel Gate Driver datasheet (Rev. A) | Jul. 29, 2020 |
Technical articles | How to achieve higher system robustness in DC drives, part 3: minimum input pulse | Sep. 19, 2018 | |
Technical articles | How to achieve higher system robustness in DC drives, part 2: interlock and deadtime | May 30, 2018 | |
Technical articles | Boosting efficiency for your solar inverter designs | May 24, 2018 | |
Technical articles | How to achieve higher system robustness in DC drives, part 1: negative voltage | Apr. 17, 2018 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Hardware development
Description
Features
- High-performance isolated driver with input and output interface
- Ability to test low-voltage datasheet parameters
- Ability to compare performance of various drivers with compatible pinout
Design tools & simulation
Features
- Leverages Cadence PSpice Technology
- Preinstalled library with a suite of digital models to enable worst-case timing analysis
- Dynamic updates ensure you have access to most current device models
- Optimized for simulation speed without loss of accuracy
- Supports simultaneous analysis of multiple products
- (...)
CAD/CAE symbols
Package | Pins | Download |
---|---|---|
SOIC (DWK) | 14 | View options |
Ordering & quality
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
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Support & training
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