The UCC27511/2 single-channel high-speed low-side gate-driver device is capable of effectively driving MOSFET and IGBT power switches. Using a design that inherently minimizes shoot-through current, the UCC27511 device is capable of sourcing and sinking high peak-current pulses into capacitive loads offering rail-to-rail drive capability and extremely small propagation delay of 13 ns (typical).
The UCC27511 device provides 4-A source, 8-A sink (asymmetrical drive) peak-drive current capability. Strong sink capability in asymmetrical drive boosts immunity against parasitic, Miller turnon effect. The UCC27511 device also features a unique split output configuration where the gate-drive current is sourced through the OUTH pin and sunk through the OUTL pin. This unique pin arrangement allows the user to apply independent turnon and turnoff resistors to the OUTH and OUTL pins (respectively) and easily control the switching slew rates.
Alternatively the OUTH and OUTL pins can be tied together, which results in a typical gate driver output configuration where the source and sink currents are delivered from the same pin. In case of UCC27511 device, the state of the device's output is simply determined by the combined states of the OUTH and OUTL pins when tied together. Output high implies that OUTH pin is pulled close to VDD pin bias voltage while OUTL pin is in high-impedance state. Similarly output low implies that OUTL pin is pulled close to the GND pin while OUTH pin is in high-impedance state. OUTH pulled to VDD, while OUTL pulled to GND pin simultaneously is not a valid state for the device.
The UCC27511 device is designed to operate over a wide VDD range of 4.5 to 18 V and wide temperature range of –40°C to 140°C. Internal undervoltage lockout (UVLO) circuitry on the VDD pin holds the output low outside VDD operating range. The capability to operate at low voltage levels, such as below 5 V, along with best-in-class switching characteristics, is especially suited for driving emerging wide band-gap power-switching devices such as GaN power-semiconductor devices.
The UCC27511 device features a dual-input design which offers flexibility of implementing both inverting (IN– pin) and noninverting (IN+ pin) configuration with the same device. Either the IN+ or IN– pin can be used to control the state of the driver output. The unused input pin can be used for enable and disable functions. For system robustness, internal pullup and pulldown resistors on the input pins ensure that outputs are held low when the input pins are in floating condition. Therefore the unused input pin is not left floating and must be properly biased to ensure that driver output is in enabled for normal operation.
The input pin threshold of the UCC27511A-Q1 device is based on TTL and CMOS-compatible low-voltage logic which is fixed and independent of the VDD supply voltage. Wide hysteresis between the high and low thresholds offers excellent noise immunity.
In the following sections with respect to UCC27511, the term output, or OUT refers to the combined state that results when the OUTH pin is tied directly to the OUTL pin. As stated earlier, output high, or OUT high refers to the state when the OUTH pin is pulled close to VDD pin bias voltage while the OUTL pin is in high-impedance state. Similarly output low or OUT low implies that the OUTL pin is pulled close to the GND pin while the OUTH pin is in high-impedance state.
The UCC27511 and UCC27512 devices have internal Undervoltage LockOut (UVLO) protection feature on the VDD pin supply circuit blocks. Whenever the driver is in UVLO condition (for example when VDD voltage less than VON during power up and when VDD voltage is less than VOFF during power down), this circuit holds all outputs LOW, regardless of the status of the inputs. The UVLO is typically 4.2 V with 300-mV typical hysteresis. This hysteresis prevents chatter when low VDD supply voltages have noise from the power supply and also when there are droops in the VDD bias voltage when the system commences switching and there is a sudden increase in IDD. The capability to operate at low voltage levels such as below 5 V, along with best-in-class switching characteristics, is especially suited for driving emerging GaN wide band-gap power-semiconductor devices.
For example, at power up, the UCC27511 and UCC27512 driver output remains LOW until the VDD voltage reaches the UVLO threshold. The magnitude of the OUT signal rises with VDD until steady-state VDD is reached. In the noninverting operation (PWM signal applied to IN+ pin) shown in Figure 21, the output remains LOW until the UVLO threshold is reached, and then the output is in-phase with the input. In the inverting operation (PWM signal applied to IN- pin) shown in Figure 22 the output remains LOW until the UVLO threshold is reached, and then the output is out-phase with the input. In both cases, the unused input pin must be properly biased to enable the output. Note that in these devices the output turns to high state only if IN+ pin is high and IN- pin is low after the UVLO threshold is reached.
Since the driver draws current from the VDD pin to bias all internal circuits, for the best high-speed circuit performance, two VDD-bypass capacitors are recommended to prevent noise problems. The use of surface-mount components is highly recommended. A 0.1-μF ceramic capacitor should be located as close as possible to the VDD to GND pins of the gate driver. In addition, a larger capacitor (such as 1 μF) with relatively low ESR should be connected in parallel and close proximity, in order to help deliver the high-current peaks required by the load. The parallel combination of capacitors should present a low impedance characteristic for the expected current levels and switching frequencies in the application.
The UCC27511 and UCC27512 feature very low quiescent IDD currents. The typical operating-supply current in Undervoltage LockOut (UVLO) state and fully-on state (under static and switching conditions) are summarized in Figure 5, Figure 6 and Figure 7. The IDD current when the device is fully on and outputs are in a static state (DC high or DC low, refer Figure 7) represents lowest quiescent IDD current when all the internal logic circuits of the device are fully operational. The total supply current is the sum of the quiescent IDD current, the average IOUT current due to switching, and finally any current related to pullup resistors on the unused input pin. For example, when the inverting input pin is pulled low additional current is drawn from VDD supply through the pullup resistors (refer to for the device Block Diagram). Knowing the operating frequency (fSW) and the MOSFET gate (QG) charge at the drive voltage being used, the average IOUT current can be calculated as product of QG and fSW.
A complete characterization of the IDD current as a function of switching frequency at different VDD bias voltages under 1.8-nF switching load is provided in Figure 15. The strikingly linear variation and close correlation with theoretical value of average IOUT indicates negligible shoot-through inside the gate-driver device attesting to its high-speed characteristics.
The input pins of the UCC27511 and UCC27512 devices are based on a TTL and CMOS compatible input-threshold logic that is independent of the VDD supply voltage. With a typicalyl high threshold of 2.2 V and a typically low threshold of 1.2 V, the logic-level thresholds can be conveniently driven with PWM control signals derived from 3.3-V and 5-V digital-power controllers. Wider hysteresis (1 V typical) offers enhanced noise immunity compared to traditional TTL-logic implementations, where the hysteresis is typically less than 0.5 V. This device also feature tight control of the input-pin threshold-voltage levels which eases system design considerations and ensures stable operation across temperature. The very-low input capacitance on these pins reduces loading and increases switching speed.
Whenever any of the input pins are in a floating condition, the output of the respective channel is held in the low state. This function is achieved using VDD-pullup resistors on all the inverting inputs (IN– pin) or GND-pulldown resistors on all the noninverting input pins (IN+ pin), (see the ).
The device also features a dual-input configuration with two input pins available to control the state of the output. The user has the flexibility to drive the device using either a noninverting input pin (IN+) or an inverting input pin (IN–). The state of the output pin is dependent on the bias on both the IN+ and IN– pins. For additional clarification, refer to the I/O-logic truth table (Table 3) and the typical application diagrams, (Figure 25 and Figure 26).
When an input pin is selected for PWM drive, the other input pin (the unused input pin) must be properly biased in order to enable the output. As previously stated, the unused input pin cannot remain in a floating condition because whenever any input pin is left in a floating condition the output is disabled. Alternatively, the unused input pin can effectively be used to implement an enable or disable function. The following explains this function:
The input stage of the driver is preferably driven by a signal with a short rise or fall time. Use caution whenever the driver is used with slowly varying input signals, especially in situations where the device is located in a mechanical socket or PCB layout that is not optimal:
If limiting the rise or fall times to the power device is the primary goal, then an external resistance is highly recommended between the output of the driver and the power device instead of adding delays on the input signal. This external resistor has the additional benefit of reducing part of the gate-charge related power dissipation in the gate-driver device package and transferring the power dissipation into the external resistor.
As mentioned earlier, an enable and disable function is easily implemented in UCC27511 and UCC27512 devices using the unused input pin. When the IN+ pin is pulled down to GND or the IN– pin is pulled down to VDD, the output is disabled. Thus the IN+ pin can be used like an enable pin that is based on active-high logic, while the IN– pin can be used like an enable pin that is based on active-low logic.
Figure 23 shows the output stage of the UCC27511 and UCC27512 devices. The UCC27511 and UCC27512 devices feature a unique architecture on the output stage which delivers the highest peak-source current when the peak source current is most needed during the Miller plateau region of the power switch turnon transition (when the power-switch drain or collector voltage experiences dV/dt). The device output stage features a hybrid pullup structure using a parallel arrangement of N-channel and P-channel MOSFET devices. By turning on the N-channel MOSFET during a narrow instant when the output changes state from low to high, the gate-driver device is able to deliver a brief boost in the peak-sourcing current enabling fast turnon.
The RO(H) parameter (see the Electrical Characteristics table) is a DC measurement and is representative of the on-resistance of the P-channel device only, because the N-Channel device is turned on only during output change of state from low to high. Thus the effective resistance of the hybrid pullup stage is much lower than what is represented by RO(H) parameter. The pulldown structure is composed of a N-channel MOSFET only. The RO(L) parameter (see the Electrical Characteristics table), which is also a DC measurement, is representative of true impedance of the pulldown stage in the device. In the UCC27511 and UCC27512 devices, the effective resistance of the hybrid pullup structure is approximately 2.7 × RO(L).
The UCC27511 device features a unique split output configuration where the gate-drive current is sourced through the OUTH pin and sunk through the OUTL pin. This unique pin arrangement allows users to apply independent turnon and turnoff resistors to the OUTH and OUTL pins respectively and easily control the turnon and turnoff switching dV/dt. This pin arrangement, along with the low pulldown impedance of the output driver stage, is especially useful in applications where a high C × dV/dt Miller turnon immunity is needed (such as with GaN power switches, SR MOSFETs and other applications) and the OUTL pin can be directly tied to the gate of the power device.
The UCC27511 and UCC27512 devices are capable of delivering 4-A source, 8-A sink (asymmetrical drive) at VDD equal to 12 V. Strong sink capability in asymmetrical drive results in a very-low pulldown impedance in the driver output stage which boosts immunity against parasitic, Miller turnon (C × dV/dt turnon) effect, especially where the low gate-charge MOSFETs or emerging wide band-gap GaN-power switches are used.
An example of a situation where the Miller turnon effect is a concern is synchronous rectification (SR). In an SR application, the dV/dt occurs on the MOSFET drain when the MOSFET is already held in off state by the gate driver. The current discharging the C(GD) Miller capacitance during this dV/dt is shunted by the pulldown stage of the driver. If the pulldown impedance is not low enough then a voltage spike can result in the VGS of the MOSFET, which can result in spurious turnon. This phenomenon is shown in Figure 24. The UCC27511 and UCC27512 device offers a best-in-class, 0.375-Ω (typ) pulldown impedance boosting immunity against Miller turnon.
The driver-output voltage swings between the VDD and GND pins which provides rail-to-rail operation as a result of the MOS-output stage which delivers very-low dropout. The presence of the MOSFET-body diodes also offers low impedance to switching overshoots and undershoots. In many cases, external Schottky diode clamps are eliminated. The outputs of these drivers are designed to withstand 500-mA reverse current without either damage to the device or logic malfunction.
The UCC27511 and UCC27512 driver devices feature best-in-class input-to-output propagation delay of 13 ns (typ) at VDD = 12 V, which promises the lowest level of pulse transmission distortion available from industry-standard gate-driver devices for high-frequency switching applications. As seen in Figure 14, there is very little variation of the propagation delay with temperature and supply voltage as well, offering typically less than 20-ns propagation delays across the entire range of application conditions.
The device operates in normal mode and UVLO mode. See the VDD and Undervoltage Lockout section for information on UVLO operation mode. In the normal mode the output state is dependent on states of the IN+ and IN– pins. Table 3 lists the output states for different input pin combinations.