SLUSEX2A September   2025  – September 2025 UCC27734 , UCC27735

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Dynamic Electrical Characteristics
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Stages and Interlock
      2. 6.3.2 Enable Function (UCC277x5 Only)
      3. 6.3.3 Undervoltage Lockout (UVLO)
      4. 6.3.4 Level Shifter
      5. 6.3.5 Output Stage
      6. 6.3.6 Low Propagation Delays and Tightly Matched Outputs
      7. 6.3.7 HS Node dV/dt
      8. 6.3.8 Split Grounds (COM and VSS)
      9. 6.3.9 Operation Under Negative HS Voltage Condition
    4. 6.4 Device Functional Modes
      1. 6.4.1 Input and Output Logic Table
      2. 6.4.2 Operation Under 100% Duty Cycle Condition
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Selecting HI and LI Low Pass Filter Components (RHI, RLI, CHI, CLI)
        2. 7.2.2.2 Selecting Bootstrap Capacitor (CBOOT)
        3. 7.2.2.3 Selecting VDD Bypass Capacitor (CVDD)
        4. 7.2.2.4 Selecting Bootstrap Resistor (RBOOT)
        5. 7.2.2.5 Selecting Gate Resistor RHO/RLO
        6. 7.2.2.6 Selecting Bootstrap Diode
        7. 7.2.2.7 Estimate the UCC2773x Power Losses
        8. 7.2.2.8 Application Example Schematic Note
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
      2. 8.1.2 Development Support
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.2.2.7 Estimate the UCC2773x Power Losses

The power losses of the UCC2773x (PUCC2773x) are estimated by calculating losses from several components.The combined power losses due to quiescent current (IQDD, IQBS) and no-load switching are calculated below:

Equation 16. P Q C = V D D ×   I V D D 100   k H z + I V H B 100   k H z = 15   V × 330   μ A + 275   μ A   ≈   9   m W

Refer to Figure 5-16 to find IVDD and IVHB. Static losses due to leakage current (IBL) are calculated from the HB high-voltage node as shown below:

Equation 17. P I B L = V H B ×   I B L × D = 450   V × 0.1   μ A × 0.5 ≈ 0.02   m W

Note that static losses due to IBLincrease with temperature. See Figure 5-10.

Dynamic losses incurred due to the gate charge while driving the FETs Q1 and Q2 are calculated below. Please note that this component typically dominates over the dynamic losses related to the internal VDD and VHB switching logic circuitry in the UCC2773x.

Equation 18. P Q G 1 , Q G 2 = 2 × V D D ×   Q G × f S W = 2 × 15   V × 87   n C × 100   k H z ≈ 261   m W

The dynamic losses are shared between the internal pullup and pulldown resistance of the gate driver IC, the external gate resistance, and the internal gate resistance of the switching device. The pullup resistance changes dynamically during switching, so using ROH provides for an overestimate of the gate driver power dissipation, which provides for design margin.

Equation 19. P G D = P Q G 1 , Q G 2 2 × R O H R O H + R G _ O N + R G _ i n t + R O L R O L + R G _ O F F + R G _ i n t
Equation 20. P G D = 261   m W 2 × 12.6   Ω 12.6   Ω   +   3.01   Ω   +   3.8   Ω + 1   Ω 1   Ω   +   3.01   Ω   +   3.8   Ω ≈ 102   m W

The total power losses in the gate driver IC for this example are calculated below:

Equation 21. P T o t a l _ G D ≈ P Q C +   P I B L + P G D =   9   m W + 0.02   m W + 102   m W ≈ 0.111   W