SLUSAW0C March   2012  – July 2025 UCC28070 , UCC28070A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Interleaving
      2. 6.3.2  Programming the PWM Frequency and Maximum Duty-Cycle Clamp
      3. 6.3.3  Frequency Dithering (Magnitude and Rate)
      4. 6.3.4  External Clock Synchronization
      5. 6.3.5  Multi-phase Operation
      6. 6.3.6  VSENSE and VINAC Resistor Configuration
      7. 6.3.7  VSENSE and VINAC Open-Circuit Protection
      8. 6.3.8  Current Synthesizer
      9. 6.3.9  Programmable Peak Current Limit
      10. 6.3.10 Linear Multiplier and Quantized Voltage Feed Forward
      11. 6.3.11 Enhanced Transient Response (VA Slew-Rate Correction)
      12. 6.3.12 Bias Voltages (VCC and VREF)
      13. 6.3.13 PFC Enable and Disable
      14. 6.3.14 Adaptive Soft-Start
      15. 6.3.15 PFC Start-Up Hold Off
      16. 6.3.16 Output Overvoltage Protection (OVP)
      17. 6.3.17 Zero-Power Detection
      18. 6.3.18 Thermal Shutdown
      19. 6.3.19 Current Loop Compensation
      20. 6.3.20 Voltage Loop Compensation
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Output Current Calculation
        2. 7.2.2.2 Bridge Rectifier
        3. 7.2.2.3 PFC Inductor (L1 and L2)
        4. 7.2.2.4 PFC MOSFETs (M1 and M2)
        5. 7.2.2.5 PFC Diode
        6. 7.2.2.6 PFC Output Capacitor
        7. 7.2.2.7 Current-Loop Feedback Configuration (Sizing of the Current-Transformer Turns-Ratio NCT and Current-Sense Resistor RS)
        8. 7.2.2.8 Current-Sense Offset and PWM Ramp for Improved Noise Immunity
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Revision History

Changes from Revision B (December 2023) to Revision C (July 2025)

  • Updated typographical errors and clarified text throughout the document. Combined UCC28070 information into UCC28070A data sheet.Go
  • Revised Features and Applications bullet items. Added hyper-links.Go
  • Added Wide-SOIC package pin-out view for UCC28070Go
  • Linked device numbers to respective DW and PW package thermal information.Go
  • Linked device numbers to respective fPWM limits.Go
  • Include UCC28070 at all mentions of UCC28070A throughout the data sheet.Go
  • Updated tSYNC meaning; added reference to minimum allowable pulse widthGo
  • Added falling thresholds to VINAC levels table.Go
  • Option in text for using ½ fPWM in Cpc equation. Changed equation to match calculator tool.Go
  • Remove extra factor of 2 from Io_ripple equationGo
  • Corrections to equations for Rta and CtaGo

Changes from Revision A (May 2016) to Revision B (December 2023)

  • Updated typographical errors and clarified text throughout the document.Go
  • Moved Absolute Maximum values for Supply voltage and current, Gate-drive currents, and signal-pin Currents from MIN column to MAX column Go
  • Updated Y-axis units in several figuresGo
  • Added SYNC frequency limitation note in External Clock Synchronization sectionGo
  • Added paragraph on PKLMT sub-harmonic oscillationGo
  • Added clarifying equation for kSYNC in Current Loop Compensation section; corrected gain in Current Error Amplifier diagram and equation for Rzc. Go
  • Updated gain in Voltage Error Amplifier diagram Go
  • Updated text to clarify bridge rectifier design considerationsGo
  • Updated method for calculating boost inductanceGo
  • Added additional references to Related Documentation sectionGo