SLUS794F November 2007 – April 2016 UCC28070
PRODUCTION DATA.
The UCC28070 power factor corrector IC controls two CCM (Continuous Conduction Mode) Boost PFC power stages operating 180° out of phase with each other. This interleaving action reduces the input and output ripple currents so that less EMI filtering is needed and allows operation at higher power levels than a non-interleaved solution.
The UCC28070 can operate over a wide range of frequencies, making it suitable for use with both MOSFET and IGBT power switches. Multiple UCC28070 controllers can be synchronized for use in higher power applications where more than two interleaved power stages are needed.
This device is especially suited to high-performance, high-power PFC applications where the use of Average Current Mode PWM control gives low THD.
One of the main benefits from the 180° interleaving of phases is significant reductions in the high-frequency ripple components of both the input current and the current into the output capacitor of the PFC preregulator. Compared to that of a single-phase PFC stage of equal power, the reduced ripple on the input current eases the burden of filtering conducted-EMI noise and helps reduce the EMI filter and C_{IN} sizes. Additionally, reduced high-frequency ripple current into the PFC output capacitor, C_{OUT}, helps to reduce its size and cost. Furthermore, with reduced ripple and average current in each phase, the boost inductor size can be smaller than in a single-phase design [1].
Ripple current reduction due to interleaving is often referred to as ripple cancellation, but strictly speaking, the peak-to-peak ripple is completely cancelled only at 50% duty-cycle in a 2-phase system. At duty-cycles other than 50%, ripple reduction occurs in the form of partial cancellation due to the superposition of the individual phase currents. Nevertheless, compared to the ripple currents of an equivalent single-phase PFC preregulator, those of a 2-phase interleaved design are extraordinarily smaller [1]. Independent of ripple cancellation, the frequency of the interleaved ripple, at both the input and output, is 2 × f_{PWM}.
On the input, 180° interleaving reduces the peak-to-peak ripple amplitude to ½ or less of the ripple amplitude of the equivalent single-phase current.
On the output, 180° interleaving reduces the rms value of the PFC-generated ripple current in the output capacitor by a factor of slightly more than √2, for PWM duty-cycles > 50%.
This can be seen in the following derivations, adapting the method by Erickson [2].
In a single-phase PFC preregulator, the total rms capacitor current contributed by the PFC stage at all duty-cycles can be shown to be approximated by:
In a dual-phase interleaved PFC preregulator, the total rms capacitor current contributed by the PFC stage for D > 50% can be shown to be approximated by:
In these equations, I_{O} = average PFC output load current, V_{O} = average PFC output voltage, V_{M} = peak of the input ac-line voltage, and η = efficiency of the PFC stage at these conditions. It can be seen that the quantity under the radical for i_{Crms2φ} is slightly smaller than ½ of that under the radical for i_{Crms1φ}. The rms currents shown contain both the low-frequency and the high-frequency components of the PFC output current. Interleaving reduces the high-frequency component, but not the low-frequency component.
The PWM frequency and maximum duty-cycle clamps for both GDx outputs of the UCC28070 are set through the selection of the resistors connected to the RT and DMAX pins, respectively. The selection of the RT resistor (R_{RT}) directly sets the PWM frequency (f_{PWM}).
Once R_{RT} has been determined, the D_{MAX} resistor (R_{DMX}) may be derived.
where
Frequency dithering refers to modulating the switching frequency to achieve a reduction in conducted-EMI noise beyond the capability of the line filter alone. The UCC28070 implements a triangular modulation method which results in equal time spent at every point along the switching frequency range. This total range from minimum to maximum frequency is defined as the dither magnitude, and is centered around the nominal switching frequency f_{PWM} set with R_{RT}. For example, a dither magnitude of 20 kHz on a nominal f_{PWM} of 100 kHz results in a frequency range of 100 kHz ±10 kHz. Furthermore, the programmed duty-cycle clamp set by R_{DMX} remains constant at the programmed value across the entire range of the frequency dithering.
The rate at which f_{PWM} traverses from one extreme to the other and back again is defined as the dither rate. For example, a dither rate of 1 kHz would linearly modulate the nominal frequency from 110 kHz to 90 kHz to 110 kHz once every millisecond. A good initial design target for dither magnitude is ±10% of f_{PWM}. Most boost components can tolerate such a spread in f_{PWM}. The designer can then iterate around there to find the best compromise between EMI reduction, component tolerances, and loop stability.
The desired dither magnitude is set by a resistor from the RDM pin to GND, of value calculated with Equation 5:
Once the value of R_{RDM} is determined, the desired dither rate may be set by a capacitor from the CDR pin to GND, of value calculated with Equation 6:
Frequency dithering may be fully disabled by forcing the CDR pin > 5 V or by connecting it to VREF (6 V) and connecting the RDM pin directly to GND. (If populated, the relatively high impedance of the RDM resistor may allow system switching noise to couple in and interfere with the controller timing functions if not bypassed with a low impedance path when dithering is disabled.)
If an external frequency source is used to synchronize f_{PWM} and frequency dithering is desired, the external frequency source must provide the dither magnitude and rate functions as the internal dither circuitry is disabled to prevent undesired performance during synchronization. (See External Clock Synchronization for more details.)
The UCC28070 has also been designed to be easily synchronized to almost any external frequency source. By disabling frequency dithering (pulling CDR > 5 V), the SYNC circuitry is enabled permitting the internal oscillator to be synchronized with pulses presented on the RDM pin. To ensure a precise 180° phase shift is maintained between the GDA and GDB outputs, the frequency (f_{SYNC}) of the pulses presented at the RDM pin must be at twice the desired f_{PWM}. For example, if a 100-kHz switching frequency is desired, the f_{SYNC} should be 200 kHz.
To ensure the internal oscillator does not interfere with the SYNC function, R_{RT} must be sized to set the internal oscillator frequency at least 10% below f_{SYNC}.
It must be noted that the PWM modulator gain is reduced by a factor equivalent to the scaled R_{RT} due to a direct correlation between the PWM ramp current and R_{RT}. Adjustments to the current loop gains should be made accordingly.
It must also be noted that the maximum duty-cycle clamp programmability is affected during external synchronization. The internal timing circuitry responsible for setting the maximum duty cycle is initiated on the falling edge of the synchronization pulse. Therefore, the selection of R_{DMX} becomes dependent on the synchronization pulse width (t_{SYNC}).
Consequently to minimize the impact of the t_{SYNC} it is clearly advantageous to use the smallest synchronization pulse width feasible.
NOTE
When external synchronization is used, a propagation delay of approximately 50 ns to 100 ns exists between internal timing circuits and the falling edge of the SYNC signal, which may result in reduced OFF-time at the highest of switching frequencies. Therefore, R_{DMX} should be adjusted downward slightly by (t_{SYNC} – 0.1 μs) / t_{SYNC} to compensate. At lower SYNC frequencies, this delay becomes an insignificant fraction of the PWM period, and can be neglected.
External synchronization also facilitates using more than 2 phases for interleaving. Multiple UCC28070s can easily be paralleled to add an even number of additional phases for higher-power applications. With appropriate phase-shifting of the synchronization signals, even more input and output ripple current cancellation can be obtained. (An odd number of phases can be accommodated if desired, but the ripple cancellation would not be optimal.) For 4-, 6-, or any 2 × n-phases (where n = the number of UCC28070 controllers), each controller should receive a SYNC signal which is 360/n degrees out of phase with each other. For a 4-phase application interleaving with two controllers, SYNC1 should be 180° out of phase with SYNC2 for optimal ripple cancellation. Similarly for a 6-phase system, SYNC1, SYNC2, and SYNC3 should be 120° out of phase with each other for optimal ripple cancellation.
In a multi-phase interleaved system, each current loop is independent and treated separately; however, there is only one common voltage loop. To maintain a single control loop, all VSENSE, VINAC, SS, IMO, and VAO signals are paralleled, respectively between the n controllers. Where current-source outputs are combined (SS, IMO, VAO), the calculated load impedances must be adjusted by 1/n to maintain the same performance as with a single controller.
Figure 18 illustrates the paralleling of two controllers for a 4-phase 90-degree-interleaved PFC system.
The primary purpose of the VSENSE input is to provide the voltage feedback from the output to the voltage control loop. Thus, a traditional resistor-divider network must be sized and connected between the output capacitor and the VSENSE pin to set the desired output voltage based on the 3-V regulation voltage on VSENSE.
A unique aspect of the UCC28070 is the need to place the same resistor-divider network on the V_{IN} side of the inductor to the VINAC pin. This provides the scaled input voltage monitoring needed for the linear multiplier and current synthesizer circuitry. It is not required that the actual resistance of the VINAC network be identical to the VSENSE network, but it is necessary that the attenuation (k_{R}) of the two divider networks be equivalent for proper PFC operation.
In noisy environments, it may be beneficial for small filter capacitors to be applied to the VSENSE and VINAC inputs to avoid the destabilizing effects of excessive noise on these inputs. If applied, the RC time-constant should not exceed 100 μs on the VSENSE input to avoid significant delay in the output transient response. The RC time-constant should also not exceed 100 μs on the VINAC input to avoid degrading of the wave-shape zero-crossings. Usually, a time constant of 3 / f_{PWM} is adequate to filter out typical noise on VSENSE and VINAC. Some design and test iteration may be required to find the optimal amount of filtering required in a particular application.
Both the VSENSE and VINAC pins have been designed with an internal 250-nA current sink to ensure that in the event of an open circuit at either pin, the voltage is not left undefined, and the UCC28070 remains in a safe operating mode.
One of the most prominent innovations in the UCC28070 design is the current synthesizer circuitry that synchronously monitors the instantaneous inductor current through a combination of ON-time sampling and OFF-time down-slope emulation.
During the ON-time of the GDA and GDB outputs, the inductor current is recorded at the CSA and CSB pins, respectively, through the current transformer network in each output phase. Meanwhile, the continuous monitoring of the input and output voltages through the VINAC and VSENSE pins permits the UCC28070 to internally recreate the down-slope of the inductor current during the respective OFF-time of each output. Through the selection of the RSYNTH resistor (R_{SYN}), based on Equation 12, the internal response may be adjusted to accommodate the wide range of inductances expected across the wide array of applications.
During inrush surge events at power up and AC drop-out recovery, V_{VSENSE} < V_{VINAC}, the synthesized downslope becomes zero. In this case, the synthesized inductor current remains above the IMO reference and the current loop drives the duty cycle to zero. This avoids excessive stress on the MOSFETs during the surge event. Once V_{VINAC} falls below V_{VSENSE}, the duty cycle increases until steady-state operation resumes.
where
The UCC28070 has been designed with a programmable cycle-by-cycle peak current limit dedicated to disabling either the GDA or GDB output whenever the corresponding current-sense input (CSA or CSB, respectively) rises above the voltage established on the PKLMT pin. Once an output has been disabled through the detection of peak current limit, the output remains disabled until the next clock cycle initiates a new PWM period. The programming range of the PKLMT voltage extends to upwards of 4 V to permit the full use of the 3-V average current sense signal range; however, note that the linearity of the current amplifiers begins to compress above 3.6 V.
A resistor-divider network from VREF to GND can easily program the peak current limit voltage on PKLMT, provided the total current out of VREF is less than 2 mA to avoid drooping of the 6-V VREF voltage. TI recommends a load of less than 0.5 mA, but if the resistance on PKLMT is very high, TI recommends a small filter capacitor on PKLMT to avoid operational problems in high-noise environments.
The UCC28070 multiplier generates a reference current which represents the desired wave shape and proportional amplitude of the AC input current. This current is converted to a reference voltage signal by the R_{IMO} resistor which is scaled in value to match the voltage of the current-sense signals. The instantaneous multiplier current is dependent upon the rectified, scaled input voltage V_{VINAC} and the voltage-error amplifier output V_{VAO}. V_{VINAC} conveys three pieces of information to the multiplier:
A major innovation in the UCC28070 multiplier architecture is the internal quantized V_{RMS} feed-forward (Q_{VFF}) circuitry, which eliminates the requirement for external filtering of the VINAC signal and the subsequent slow response to transient line variations. A unique circuit algorithm detects the transition of the peak of V_{VINAC} through seven thresholds and generates an equivalent VFF level centered within the 8-Q_{VFF} ranges. The boundaries of the ranges expand with increasing V_{IN} to maintain an approximately equal-percentage delta between levels. These 8-Q_{VFF} levels are spaced to accommodate the full universal line range of 85 to 265 V_{RMS}.
A great benefit of the Q_{VFF} architecture is that the fixed k_{VFF} factors eliminate any contribution to distortion of the multiplier output, unlike an externally-filtered VINAC signal which unavoidably contains 2nd-harmonic distortion components. Furthermore, the Q_{VFF} algorithm allows for rapid response to both increasing and decreasing changes in input rms voltage so that disturbances transmitted to the PFC output are minimized. 5% hysteresis in the level thresholds help avoid chattering between Q_{VFF} levels for V_{VINAC} voltage peaks near a particular threshold or containing mild ringing or distortion. The Q_{VFF} architecture requires that the input voltage be largely sinusoidal, and relies on detecting zero-crossings to adjust Q_{VFF} downward on decreasing input voltage. Zero-crossings are defined as V_{VINAC} falling below 0.7 V for at least 50 μs, typically.
Table 1 shows the relationship between the various V_{VINAC} peak voltages and the corresponding k_{VFF} terms for the multiplier equation.
LEVEL | V_{VINAC} PEAK VOLTAGE | k_{VFF} (V^{2}) | V_{IN} PEAK VOLTAGE ^{(1)} |
---|---|---|---|
8 | 2.6 V ≤ V_{VINAC(pk)} | 3.857 | >345 V |
7 | 2.25 V ≤ V_{VINAC(pk)} < 2.6 V | 2.922 | 300 V to 345 V |
6 | 1.95 V ≤ V_{VINAC(pk)} < 2.25 V | 2.199 | 260 V to 300 V |
5 | 1.65 V ≤ V_{VINAC(pk)} < 1.95 V | 1.604 | 220 V to 260 V |
4 | 1.4 V ≤ V_{VINAC(pk)} < 1.65 V | 1.156 | 187 V to 220 V |
3 | 1.2 V ≤ V_{VINAC(pk)} < 1.4 V | 0.839 | 160 V to 187 V |
2 | 1 V ≤ V_{VINAC(pk)} < 1.2 V | 0.600 | 133 V to 160 V |
1 | V_{VINAC(pk)} ≤ 1 V | 0.398 | <133 V |
The multiplier output current I_{IMO} for any line and load condition can thus be determined using Equation 13:
Because the k_{VFF} value represents the scaled (V_{RMS})^{2} at the center of a level, V_{VAO} adjusts slightly upwards or downwards when V_{VINAC(pk)} is either lower or higher than the center of the Q_{VFF} voltage range to compensate for the difference. This is automatically accomplished by the voltage loop control when V_{IN} varies, both within a level and after a transition between levels.
The output of the voltage-error amplifier (V_{VAO}) is clamped at 5 V, which represents the maximum PFC output power. This value is used to calculate the maximum reference current at the IMO pin, and sets a limit for the maximum input power allowed (and, as a consequence, limits maximum output power).
Unlike a continuous V_{FF} situation, where maximum input power is a fixed power at any V_{RMS} input, the discrete Q_{VFF} levels permit a variation in maximum input power within limited boundaries as the input V_{RMS} varies within each level.
The lowest maximum power limit occurs at the V_{VINAC} voltage of 0.76 V, while the highest maximum power limit occurs at the increasing threshold from level-1 to level-2. This pattern repeats at every level transition threshold, considering that decreasing thresholds are 95% of the increasing threshold values. Below V_{VINAC} = 0.76 V, P_{IN} is always less than P_{IN(max)}, falling linearly to zero with decreasing input voltage.
For example, to design for the lowest maximum power allowable, determine the maximum steady-state (average) output power required of the PFC preregulator and add some additional percentage to account for line drop-out recovery power (to recharge C_{OUT} while full load power is drawn) such as 10% or 20% of P_{OUT(max)}. Then apply the expected efficiency factor to find the lowest maximum input power allowable:
At the P_{IN(max)} design threshold, V_{VINAC} = 0.76 V, hence Q_{VFF} = 0.398 and input V_{AC} = 73 V_{RMS} (accounting for 2‑V bridge-rectifier drop) for a nominal 400-V output system.
This I_{IN(pk)} value represents the combined average current through the boost inductors at the peak of the line voltage. Each inductor current is detected and scaled by a current-sense transformer (CT). Assuming equal currents through each interleaved phase, the signal voltage at each current sense input pin (CSA and CSB) is developed across a sense resistor selected to generate approximately 3 V based on ½I_{IN(pk)} × R_{S} / N_{CT}, where R_{S} is the current sense resistor and N_{CT} is the CT turns-ratio.
I_{IMO} is then calculated at that same lowest maximum-power point, as:
R_{IMO} is selected such that:
Therefore:
At the increasing side of the level-1 to level-2 threshold, note that the IMO current would allow higher input currents at low-line:
However, this current may easily be limited by the programmable peak current limiting (PKLMT) feature of the UCC28070 if required by the power stage design.
The same procedure can be used to find the lowest and highest input power limits at each of the Q_{VFF} level transition thresholds. At higher line voltages, where the average current with inductor ripple is traditionally below the PKLMT threshold, the full variation of maximum input power is seen, but the input currents are inherently below the maximum acceptable current levels of the power stage.
The performance of the multiplier in the UCC28070 has been significantly enhanced when compared to previous generation PFC controllers, with high linearity and accuracy over most of the input ranges. The accuracy is at its worst as V_{VAO} approaches 1 V because the error of the (V_{VAO} – 1) subtraction increases and begins to distort the IMO reference current to a greater degree.
Due to the low-voltage loop bandwidth required to maintain proper PFC and ignore the slight ripple at twice line frequency on the output, the response of ordinary controllers to input voltage and load transients are also slow. However, the Q_{VFF} function effectively handles the line transient response with the exception of any minor adjustments needed within a Q_{VFF} level. Load transients on the other hand can only be handled by the voltage loop; therefore, the UCC28070 has been designed to improve its transient response by pulling up on the output of the voltage amplifier (V_{VAO}) with an additional 100 μA of current in the event the voltage on VSENSE drops below 93% of regulation (2.79 V). During a soft-start cycle, when V_{VSENSE} is ramping up from the 0.75-V PFC Enable threshold, the 100-μA correction current source is disabled to ensure the gradual and controlled ramping of output voltage and current during a soft start.
The UCC28070 operates within a V_{CC} bias supply range of 10 V to 21 V. An undervoltage lockout (UVLO) threshold prevents the PFC from activating until V_{CC} > 10.2 V, and 1 V of hysteresis assures reliable start-up from a possibly low-compliance bias source. An internal 25-V Zener-like clamp on the VCC pin is intended only to protect the device from brief energy-limited surges from the bias supply, and should not be used as a regulator with a current-limited source.
At minimum, a 0.1-μF ceramic bypass capacitor must be applied from VCC to GND close to the device pins to provide local filtering of the bias supply. Larger values may be required depending on I_{CC} peak current magnitudes and durations to minimize ripple voltage on VCC.
To provide a smooth transition out of UVLO and to make the 6-V voltage reference available as early as possible, the output from VREF is enabled when V_{CC} exceeds 8 V typically.
The VREF circuitry is designed to provide the biasing of all internal control circuits and for limited use externally. At minimum, a 22-nF ceramic bypass capacitor must be applied from VREF to GND close to the device pins to ensure stability of the circuit. External load current on the VREF pin should be limited to less than 2 mA, or degraded regulation may result.
The UCC28070 contains two independent circuits dedicated to disabling the GDx outputs based on the biasing conditions of the VSENSE or SS pins. The first is a PFC Enable which monitors V_{VSENSE} and holds off soft-start and the overall PFC function until the output has pre-charged to approximately 25%. Prior to V_{VSENSE} reaching 0.75 V, almost all of the internal circuitry is disabled. Once V_{VSENSE} reaches 0.75 V and V_{VAO} < 0.75 V, the oscillator, multiplier, and current synthesizer are enabled and the SS circuitry begins to ramp up the voltage on the SS pin. The second circuit provides an external interface to emulate an internal fault condition to disable the GDx output without fully disabling the voltage loop and multiplier. By externally pulling the SS pin below 0.6 V, the GDx outputs are immediately disabled and held low. Assuming no other fault conditions are present, normal PWM operation resumes when the external SS pulldown is released. The external pulldown must be sized large enough to override the internal 1.5-mA adaptive SS pullup once the SS voltage falls below the disable threshold. TI recommends using a MOSFET with less than 100-Ω R_{DS(on)} resistance to ensure the SS pin is held adequately below the disable threshold.
To maintain a controlled power up, the UCC28070 has been designed with an adaptive soft-start function that overrides the internal reference voltage with a controlled voltage ramp during power up. On initial power up, once V_{VSENSE} exceeds the 0.75-V enable threshold (V_{EN}), the internal pulldown on the SS pin is released, and the 1.5‑mA adaptive soft-start current source is activated. This 1.5-mA pull-up almost immediately pulls the SS pin to 0.75 V (V_{VSENSE}) to bypass the initial 25% of dead time during a traditional 0 V to Vregulation SS ramp. Once the SS pin has reached the voltage on VSENSE, the 10-μA soft-start current (I_{SS}) takes over. Thus, through the selection of the soft-start capacitor (C_{SS}), the effective soft-start time (t_{SS}) may be easily programmed based on Equation 21.
Often, a system restart is desired following a brief shut-down. In such a case, VSENSE may still have substantial voltage if V_{OUT} has not fully discharged or if high line has peak charged C_{OUT}. To eliminate the delay caused by charging C_{SS} from 0 V up to the precharged V_{VSENSE} with only the 10-μA current source and minimize any further output voltage sag, the adaptive soft start uses a 1.5-mA current source to rapidly charge C_{SS} to V_{VSENSE}, after which time the 10-μA source controls the V_{SS} rise at the desired soft-start ramp rate. In such a case, t_{SS} is estimated as follows:
where
NOTE
For soft start to be effective and avoid overshoot on V_{OUT}, the SS ramp must be slower than the voltage-loop control response. Choose C_{SS} ≥ C_{VZ} to ensure this.
An additional feature designed into the UCC28070 is the Start-Up Hold Off logic that prevents the device from initiating a soft-start cycle until the VAO pin is below the zero-power threshold (0.75 V). This feature ensures that the SS cycle initiates from zero-power and zero duty-cycle while preventing the potential for any significant inrush currents due to stored charge in the VAO compensation network.
Because of the high voltage output and a limited design margin on the output capacitor, output overvoltage protection is essential for PFC circuits. The UCC28070 implements OVP through the continuous monitoring of V_{VSENSE}. In the event V_{VSENSE} rises above 106% of regulation (3.18 V), the GDx outputs are immediately disabled to prevent the output voltage from reaching excessive levels. Meanwhile the CAOx outputs are pulled low to ensure a controlled recovery starting from 0% duty-cycle after an OVP fault is released. Once V_{VSENSE} has dropped below 3.08 V, the PWM operation resumes normal operation.
To prevent undesired performance under no-load and near no-load conditions, the UCC28070 zero-power detection comparator is designed to disable both GDA and GDB outputs in the event V_{VAO} voltage falls below 0.75 V. The 150 mV of hysteresis ensures that the outputs remain disabled until V_{VAO} has nearly risen back into the linear range of the multiplier (V_{VAO} ≥ 0.9 V).
To protect the power supplies from silicon failures at excessive temperatures, the UCC28070 has an internal temperature-sensing comparator that shuts down nearly all of the internal circuitry, and disables the GDA and GDB outputs, if the die temperature rises above 160°C. Once the die temperature falls below 140°C, the device brings the outputs up through a typical soft start.
The UCC28070 incorporates two identical and independent transconductance-type current-error amplifiers (one for each phase) with which to control the shaping of the PFC input current waveform. The current-error amplifier (CA) forms the heart of the embedded current control loop of the boost PFC preregulator, and is compensated for loop stability using familiar principles [4, 5]. The output of the CA for phase-A is CAOA, and that for phase-B is CAOB. Because the design considerations are the same for both, they are collectively referred to as CAOx, where x is A or B.
In a boost PFC preregulator, the current control loop comprises the boost power plant stage, the current sensing circuitry, the wave-shape reference, the PWM stage, and the CA with compensation components. The CA compares the average boost inductor current sensed with the wave-shape reference from the multiplier stage and generates an output current proportional to the difference.
This CA output current flows through the impedance of the compensation network generating an output voltage, V_{CAO}, which is then compared with a periodic voltage ramp to generate the PWM signal necessary to achieve PFC.
For frequencies above boost LC resonance and below f_{PWM}, the small-signal model of the boost stage, which includes current sensing, can be simplified to:
where
An R_{ZC}C_{ZC} network is introduced on CAOx to obtain high gain for the low-frequency content of the inductor current signal, but reduced flat gain above the zero frequency out to f_{PWM} to attenuate the high-frequency switching ripple content of the signal (thus averaging it).
The switching ripple voltage should be attenuated to less than 1/10 of the ΔV_{RMP} amplitude so as to be considered negligible ripple.
Thus, CAOx gain at f_{PWM} is:
where
The current-loop cross-over frequency is then found by equating the open loop gain to 1 and solving for f_{CXO}:
C_{CZ} is then determined by setting f_{ZC} = f_{CXO} = 1 / (2πR_{ZC} × C_{ZC}) and solving for C_{ZC}. At f_{ZC} = f_{CXO}, a phase margin of 45° is obtained at f_{CXO}. Greater phase margin may be had by placing f_{ZC} < f_{CXO}.
An additional high-frequency pole is generally added at f_{PWM} to further attenuate ripple and noise at f_{PWM} and higher. This is done by adding a small-value capacitor, C_{pc}, across the R_{zc}C_{zc}network.
The procedure above is valid for fixed-value inductors.
NOTE
If a swinging-choke boost inductor (inductance decreases with increasing current) is used, f_{CXO} varies with inductance, so C_{ZC} should be determined at maximum inductance.
The outer voltage control loop of the dual-phase PFC controller functions the same as with a single-phase controller, and compensation techniques for loop stability are standard [4]. The bandwidth of the voltage-loop must be considerably lower than the twice-line ripple frequency (f_{2LF}) on the output capacitor to avoid distortion-causing correction to the output voltage. The output of the voltage-error amplifier (V_{VAO}) is an input to the multiplier to adjust the input current amplitude relative to the required output power. Variations on VAO within the bandwidth of the current loops influences the wave-shape of the input current. Because the low-frequency ripple on C_{OUT} is a function of input power only, its peak-to-peak amplitude is the same at high-line as at low-line. Any response of the voltage-loop to this ripple has a greater distorting effect on high-line current than on low-line current. Therefore, the allowable percentage of 3rd-harmonic distortion on the input current contributed by VAO should be determined using high-line conditions.
Because the voltage-error amplifier (VA) is a transconductance type of amplifier, the impedance on its input has no bearing on the amplifier gain, which is determined solely by the product of its transconductance (g_{mv}) with its output impedance (Z_{OV}). Thus, the VSENSE input divider-network values are determined separately based on criteria discussed in VSENSE and VINAC Resistor Configuration. Its output is the VAO pin.
The twice-line ripple voltage component of V_{VSENSE} must be sufficiently attenuated and phase-shifted at VAO to achieve the desired level of 3rd-harmonic distortion of the input current wave-shape [4]. For every 1% of 3rd-harmonic input distortion allowable, the small-signal gain G_{VEA} = V_{VAOpk} / v_{SENSEpk} = g_{mv} × Z_{OV} at the twice-line frequency should allow no more than 2% ripple over the full V_{VAO} voltage range. In the UCC28070, V_{VAO} can range from 1 V at zero load power to ~4.2 V at full load power for a ΔV_{VAO} = 3.2 V, so 2% of 3.2 V is 64-mV peak ripple.
NOTE
Although the maximum V_{VAO} is clamped at 5 V, at full load V_{VAO} may vary around an approximate center point of 4.2 V to compensate for the effects of the quantized feed-forward voltage in the multiplier stage (see Linear Multiplier and Quantized Voltage Feed Forward for details). Therefore, 4.2 V is the proper voltage to use to represent maximum output power when performing voltage-loop gain calculations.
The output capacitor maximum low-frequency, zero-to-peak, ripple voltage is closely approximated by:
where
where
Thus, for k_{3rd}, the percentage of allowable 3rd-harmonic distortion on the input current attributable to the VAO ripple,
This impedance on VAO is set by a capacitor (C_{PV}), where C_{PV} = 1 / (2πf_{2LF} × Z_{OV}(f_{2LF})); therefore:
The voltage-loop unity-gain cross-over frequency (f_{VXO}) may now be solved by setting the open-loop gain equal to 1:
The zero-resistor (R_{ZV}) from the zero-placement network of the compensation may now be calculated. Together with C_{PV}, R_{ZV} sets a pole right at f_{VXO} to obtain 45° phase margin at the cross-over.
Finally, a zero is placed at or below f_{VXO} / 6 with capacitor C_{ZV} to provide high gain at DC but with a breakpoint far enough below f_{VXO} so as not to significantly reduce the phase margin. Choosing f_{VXO} / 10 allows one to approximate the parallel combination value of C_{ZV} and C_{PV} as C_{ZV}, and solve for C_{ZV} simply as:
By using a spreadsheet or math program, C_{ZV}, R_{ZV}, and C_{PV} may be manipulated to observe their effects on f_{VXO} and phase margin and the percentage contribution to 3rd-harmonic distortion. Also, phase margin may be checked as P_{IN(avg) }level and system parameter tolerances vary.
NOTE
The percent of 3rd-harmonic distortion calculated in this section represents the contribution from the f_{2LF} voltage ripple on C_{OUT} only. Other sources of distortion, such as the current-sense transformer, the current synthesizer stage, even distorted V_{IN}, and so on, can contribute additional 3rd and higher order harmonic distortion.
The UCC28070 operates in Average Current Mode. This eliminates the peak-to-average current error inherent in the peak current mode control method and gives lower THD and harmonics on the current drawn from the line. It does not require slope compensation and has better noise immunity than the peak current control method.