SGLS183C August   2003  – July 2025 UCC2808A-1Q1 , UCC2808A-2Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configurations and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Pin Descriptions
        1. 7.3.1.1 COMP Pin
        2. 7.3.1.2 OUTA and OUTB Pins
        3. 7.3.1.3 RC Pin
        4. 7.3.1.4 VDD Pin
    4. 7.4 Device Functional Modes
      1. 7.4.1 VCC
      2. 7.4.2 Push-Pull or Half-Bridge Function
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

TA = –40°C to 125°C for the UCC2808A-xQ1, VDD = 10V(1), 1μF capacitor from VDD to GND, R = 22kΩ, C = 330pF TA = TJ, (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
OSCILLATOR SECTION
Oscillator frequency175194213kHz
Oscillator amplitude/VDD(2)0.440.50.56V/V
ERROR AMPLIFIER SECTION
Input voltageCOMP = 2V1.9522.05V
Input bias current–11µA
Open loop voltage gain6080dB
COMP sink currentFB = 2.2V, COMP = 1V0.32.5mA
COMP source currentFB = 1.3V, COMP = 3.5V–0.2–0.5mA
PWM SECTION
Maximum duty cycleMeasured at OUTA or OUTB484950%
Minimum duty cycleCOMP = 0V0%
CURRENT SENSE SECTION
Gain(3)1.92.22.5V/V
Maximum input signalCOMP = 5V(4)0.450.50.55V
CS to output delayCOMP = 3.5V, CS from 0mV to 600mV100200ns
CS source current–200nA
CS sink currentCS = 0.5V, RC = 5.5V(5)410mA
Over current threshold0.650.750.85V
COMP to CS offsetCS = 0V0.350.81.2V
OUTPUT SECTION
OUT low levelI = 100mA0.51.1V
OUT high levelI = −50mA, VDD – OUT0.51V
Rise timeCL = 1nF2560ns
Fall timeCL = 1nF2560ns
UNDERVOLTAGE LOCKOUT SECTION
Start thresholdUCC2808A−1(1)11.512.513.5V
UCC2808A−24.14.34.5V
Minimum operating voltage after startUCC2808A−17.68.39V
UCC2808A−23.94.14.3V
HysteresisUCC2808A−13.54.25.1V
UCC2808A−20.10.20.3V
SOFT START SECTION
COMP rise timeFB = 1.8V, rise from 0.5V to 4V3.520ms
OVERALL SECTION
Startup currentVDD < start threshold130260µA
Operating supply currentFB = 0V, CS = 0V(6)(1)12mA
VDD zener shunt voltageIDD = 10mA(7)131415V
(1) For UCC2808A−1Q1, set VDD above the start threshold before setting at 10V.
(2) Measured at RC. Signal amplitude tracks VDD.
(3) Gain is defined by: A = ∆VCOMP/∆VCS, 0 ≤ VCS ≤ 0.4V.
(4) Parameter measured at trip point of latch with FB at 0V.
(5) The internal current sink on the CS pin is designed to discharge an external filter capacitor. The pin is not intended to be a DC sink path.
(6) Does not include current in the external oscillator network.
(7) Start threshold and zener shunt threshold track one another.