SLUS161G April   1999  – April 2025 UCC2813-0 , UCC2813-1 , UCC2813-2 , UCC2813-3 , UCC2813-4 , UCC2813-5 , UCC3813-0 , UCC3813-1 , UCC3813-2 , UCC3813-3 , UCC3813-4 , UCC3813-5

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Detailed Pin Descriptions
        1. 7.3.1.1 COMP
        2. 7.3.1.2 CS
        3. 7.3.1.3 FB
        4. 7.3.1.4 GND
        5. 7.3.1.5 OUT
        6. 7.3.1.6 RC
        7. 7.3.1.7 REF
        8. 7.3.1.8 VCC
      2. 7.3.2  Undervoltage Lockout (UVLO)
      3. 7.3.3  Self-Biasing, Active Low Output
      4. 7.3.4  Reference Voltage
      5. 7.3.5  Oscillator
      6. 7.3.6  Synchronization
      7. 7.3.7  PWM Generator
      8. 7.3.8  Minimum Off-Time Adjustment (Dead-Time Control)
      9. 7.3.9  Leading Edge Blanking
      10. 7.3.10 Minimum Pulse Width
      11. 7.3.11 Current Limiting
      12. 7.3.12 Overcurrent Protection and Full-Cycle Restart
      13. 7.3.13 Soft Start
      14. 7.3.14 Slope Compensation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 UVLO Mode
      3. 7.4.3 Soft-Start Mode
      4. 7.4.4 Fault Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Bulk Capacitor Calculation
        2. 8.2.2.2  Transformer Design
        3. 8.2.2.3  MOSFET and Output Diode Selection
        4. 8.2.2.4  Output Capacitor Calculation
        5. 8.2.2.5  Current Sensing Network
        6. 8.2.2.6  Gate Drive Resistor
        7. 8.2.2.7  REF Bypass Capacitor
        8. 8.2.2.8  RT and CT
        9. 8.2.2.9  Start-Up Circuit
        10. 8.2.2.10 Voltage Feedback Compensation Procedure
          1. 8.2.2.10.1 Power Stage Gain, Zeroes, and Poles
          2. 8.2.2.10.2 Compensating the Loop
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Related Links
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
  • PW|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

Unless otherwise stated, these specifications apply for –40°C ≤ TA ≤ 85°C for the UCC2813-x device; 0°C ≤ TA ≤ 70°C for the UCC3813-x device, TJ = TA; VVCC = 10 V(1); RT = 100 kΩ from REF to RC; CT = 330 pF from RC to GND; 0.1-µF capacitor from VCC to GND; 0.1-µF capacitor from VREF to GND.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
REFERENCE
Output voltage TJ = 25°C, I = 0.2 mA, UCCx813-[0,1,2,4] 4.925 5 5.075 V
TJ = 25°C, I = 0.2 mA, UCCx813-[3,5] 3.94 4 4.06
Load regulation 0.2 mA < I < 5 mA 10 30 mV
Total variation UCCx813-[0,1,2,4](5) 4.84 5 5.1 V
UCCx813-[3,5](5) 3.84 4 4.08
Output noise voltage 10 Hz ≤ f ≤ 10 kHz, TJ = 25°C(7) 70 µV
Long term stability TA = 125°C, 1000 hours(7) 5 mV
Output short circuit –5 –35 mA
OSCILLATOR
Oscillator frequency UCCx813-[0,1,2,4](2) 40 46 52 kHz
UCCx813-[3,5](2) 26 31 36
Temperature stability See note (7) 2.5%
Amplitude peak-to-peak 2.25 2.4 2.55 V
Oscillator peak voltage 2.45 V
ERROR AMPLIFIER
Input voltage VCOMP = 2.5 V; UCCx813-[0,1,2,4] 2.42 2.5 2.56 V
VCOMP = 2 V; UCCx813-[3,5] 1.92 2 2.05
Input bias current –2 2 µA
Open loop voltage gain 60 80 dB
COMP sink current VFB = 2.7 V, VCOMP = 1.1 V 0.4 2.5 mA
COMP source current VFB = 1.8 V, VCOMP = VREF – 1.2 V –0.2 –0.5 –0.8 mA
Gain-bandwidth product See note (7) 2 MHz
PWM
Maximum duty cycle UCCx813-[0,2,3] 97% 99% 100%
UCCx813-[1,4,5] 48% 49% 50%
Minimum duty cycle VCOMP = 0 V 0%
CURRENT SENSE
Gain See note (3) 1.1 1.65 1.8 V/V
Maximum input signal VCOMP = 5 V(4) 0.9 1 1.1 V
Input bias current –200 200 nA
CS blank time 50 100 150 ns
Overcurrent threshold 1.32 1.55 1.7 V
COMP to CS offset VCS = 0 V 0.45 0.9 1.35 V
OUTPUT
OUT low level I = 20 mA, all parts 0.1 0.4 V
I = 200 mA, all parts 0.35 0.9
I = 50 mA, VVCC = 5 V, UCCx813-[3,5] 0.15 0.4
I = 20 mA, VCC = 0 V, all parts 0.7 1.2
VVCC – OUT OUT high Vsat I = –20 mA, all parts 0.15 0.4 V
I = –200 mA, all parts 1 1.9
I = –50 mA, VVCC = 5 V, UCCx813-[3,5] 0.4 0.9
Rise time CL = 1 nF 41 70 ns
Fall time CL = 1 nF 44 75 ns
UNDERVOLTAGE LOCKOUT
Start threshold (6) UCCx813-0 6.6 7.2 7.8 V
UCCx813-1 8.6 9.4 10.2
UCCx813-[2,4] 11.5 12.5 13.5
UCCx813-[3,5] 3.7 4.1 4.5
Stop threshold (6) UCCx813-0 6.3 6.9 7.5 V
UCCx813-1 6.8 7.4 8
UCCx813-[2,4] 7.6 8.3 9
UCCx813-[3,5] 3.2 3.6 4
Start to stop hysteresis UCCx813-0 0.12 0.3 0.48 V
UCCx813-1 1.6 2 2.4
UCCx813-[2,4] 3.5 4.2 5.1
UCCx813-[3,5] 0.2 0.5 0.8
SOFT START
COMP rise time VFB = 1.8 V, Rise from 0.5 V to REF – 1 V 4 ms
OVERALL
Start-up current VVCC < start threshold 0.1 0.23 mA
Operating supply current VFB = 0 V, VCS = 0 V, VRC = 0 V 0.5 1.2 mA
VCC internal Zener voltage(6) ICC = 10 mA 12 13.5 15 V
VCC internal Zener voltage minus start-threshold voltage (6) UCCx813-[2,4] 0.5 1 V
(1) Adjust VCC above the start threshold before setting at 10 V.
(2) Output frequency for the UCCx813-[0,2,3] device is the oscillator frequency. Output frequency for the UCCx813-[1,4,5] device is one-half the oscillator frequency.
(3) Gain is defined by: UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5 UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5 .
(4) Parameter measured at trip point of latch with FB at 0 V.
(5) Total variation includes temperature stability and load regulation.
(6) Start threshold, stop threshold, and Zener-shunt thresholds track one another.
(7) Ensured by design. Not 100% tested in production.