SLUS161F April   1999  – May 2020 UCC2813-0 , UCC2813-1 , UCC2813-2 , UCC2813-3 , UCC2813-4 , UCC2813-5 , UCC3813-0 , UCC3813-1 , UCC3813-2 , UCC3813-3 , UCC3813-4 , UCC3813-5

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Block Diagram
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Detailed Pin Descriptions
        1. 8.3.1.1 COMP
        2. 8.3.1.2 CS
        3. 8.3.1.3 FB
        4. 8.3.1.4 GND
        5. 8.3.1.5 OUT
        6. 8.3.1.6 RC
        7. 8.3.1.7 REF
        8. 8.3.1.8 VCC
      2. 8.3.2  Undervoltage Lockout (UVLO)
      3. 8.3.3  Self-Biasing, Active Low Output
      4. 8.3.4  Reference Voltage
      5. 8.3.5  Oscillator
      6. 8.3.6  Synchronization
      7. 8.3.7  PWM Generator
      8. 8.3.8  Minimum Off-Time Adjustment (Dead-Time Control)
      9. 8.3.9  Leading Edge Blanking
      10. 8.3.10 Minimum Pulse Width
      11. 8.3.11 Current Limiting
      12. 8.3.12 Overcurrent Protection and Full-Cycle Restart
      13. 8.3.13 Soft Start
      14. 8.3.14 Slope Compensation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation
      2. 8.4.2 UVLO Mode
      3. 8.4.3 Soft-Start Mode
      4. 8.4.4 Fault Mode
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Bulk Capacitor Calculation
        2. 9.2.2.2  Transformer Design
        3. 9.2.2.3  MOSFET and Output Diode Selection
        4. 9.2.2.4  Output Capacitor Calculation
        5. 9.2.2.5  Current Sensing Network
        6. 9.2.2.6  Gate Drive Resistor
        7. 9.2.2.7  REF Bypass Capacitor
        8. 9.2.2.8  RT and CT
        9. 9.2.2.9  Start-Up Circuit
        10. 9.2.2.10 Voltage Feedback Compensation Procedure
          1. 9.2.2.10.1 Power Stage Gain, Zeroes, and Poles
          2. 9.2.2.10.2 Compensating the Loop
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
  • P|8
  • PW|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Compensating the Loop

For good transient response, the bandwidth of the finalized design must be as wide as possible. The bandwidth of a CCM flyback (fBW) is limited to ¼ of the RHP-zero frequency, or approximately 1.9 kHz using Equation 33.

Equation 33. UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5 UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5 Equation_34_SLUS270.gif

The gain of the open-loop power stage at fBW is equal to –22.4 dB and the phase at fBW is equal to –87°. First step is to choose the output voltage-sensing resistor values. The output sensing resistors are selected based on the allowed power consumption and in this case, 1 mA of sensing current is assumed.

The TL431 is used as the feedback amplifier. Given its 2.5-V reference voltage, the voltage-sensing dividers RFBU and RFBB can be selected with Equation 34 and Equation 35.

Equation 34. UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5 UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5 Equation_35_SLUS270.gif
Equation 35. UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5 UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5 Equation_36_SLUS270.gif

Next step is to put the compensator zero fCZ at 190 Hz, which is 1/10 of the target crossover frequency. Choose CZ as a fixed value of 10 nF and choose the zero resistor value according to Equation 36.

Equation 36. UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5 UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5 Equation_37_SLUS270.gif

Next, place a pole at the lower of RHP-zero or the ESR-zero frequencies. Based previous analysis, the RHP zero is at 7.65 kHz and the ESR zero is at 6 kHz, so the pole of the compensation loop should be put at 6 kHz. This pole can be added through the primary side error amplifier. RFB and CFB provide the necessary pole. Choosing RFB as 10 kΩ, CFB is calculated by Equation 37.

Equation 37. UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5 UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5 Equation_38_SLUS270.gif

Based on the compensation loop structure, the entire compensation loop transfer function is written as Equation 38.

Equation 38. UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5 UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5 Eqn_40_SLUS161.gif

where

  • CTR is the current transfer ratio of the opto-coupler. Choose 1 as the nominal value for CTR.
  • REG is the opto-emitter pulldown resistor and 1 kΩ is chosen as a default value

The only remaining unknown value required in this equation is RLED. The entire loop gain must be equal to 1 at the crossover frequency. RLED is calculated accordingly as 1.62 kΩ.

The final closed-loop Bode plots are shown in Figure 36 and Figure 37. The converter achieves approximately 2-kHz crossover frequency and approximately 70° of phase margin.

TI recommends checking the loop stability across all the corner cases, including component tolerances, to ensure system stability.

UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5 UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5 Figure_36A_SLUS270E.gifFigure 36. Converter Closed-Loop Bode Plot: Gain
UCC2813-0 UCC2813-1 UCC2813-2 UCC2813-3 UCC2813-4 UCC2813-5 UCC3813-0 UCC3813-1 UCC3813-2 UCC3813-3 UCC3813-4 UCC3813-5 Figure_36B_SLUS270E.gifFigure 37. Converter Closed-Loop Bode Plot: Phase