SLUSBL7B December   2013  – October 2015 UCC28722

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Bias Voltage Supply (VDD)
      2. 7.3.2 Ground (GND)
      3. 7.3.3 Voltage-Sense (VS)
      4. 7.3.4 Base Drive (DRV)
      5. 7.3.5 Current Sense (CS)
        1. 7.3.5.1 Example
      6. 7.3.6 Cable Compensation (CBC)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Primary-Side Voltage Regulation
      2. 7.4.2 Primary-Side Current Regulation
      3. 7.4.3 Valley Switching
      4. 7.4.4 Start-Up Operation
      5. 7.4.5 Fault Protection
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Stand-by Power Estimate
        2. 8.2.2.2 Input Bulk Capacitance and Minimum Bulk Voltage
        3. 8.2.2.3 Transformer Turns Ratio, Inductance, Primary-Peak Current
        4. 8.2.2.4 Transformer Parameter Verification
        5. 8.2.2.5 Output Capacitance
        6. 8.2.2.6 VDD Capacitance, CDD
        7. 8.2.2.7 VS Resistor Divider, Line Compensation, and Cable Compensation
        8. 8.2.2.8 Startup Resistance and Startup Time
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
        1. 11.1.1.1 Definition of Terms
          1. 11.1.1.1.1  Capacitance Terms in Farads
          2. 11.1.1.1.2  Duty Cycle Terms
          3. 11.1.1.1.3  Frequency Terms in Hertz
          4. 11.1.1.1.4  Current Terms in Amperes
          5. 11.1.1.1.5  Current and Voltage Scaling Terms
          6. 11.1.1.1.6  Transformer Terms
          7. 11.1.1.1.7  Power Terms in Watts
          8. 11.1.1.1.8  Resistance Terms in Ω
          9. 11.1.1.1.9  Timing Terms in Seconds
          10. 11.1.1.1.10 Voltage Terms in Volts
          11. 11.1.1.1.11 AC Voltage Terms in VRMS
          12. 11.1.1.1.12 Efficiency Terms
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VVDD Bias supply voltage, VDD 38 V
IDRV Continuous base current sink 50 mA
IDRV Continuous base current source Self-limiting mA
IVS Peak current, VS –1.2 mA
VDRV Base drive voltage at DRV –0.5 Self-limiting V
Voltage VS –0.75 7 V
CS, CBC –0.5 5 V
TJ Operating junction temperature –55 150 °C
Lead temperature 0.6 mm from case for 10 seconds 260 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDD Bias supply operating voltage 9 35 V
CVDD VDD bypass capacitor 1.0 10 µF
RCBC Cable-compensation resistance 10 kΩ
IVS VS pin current −1 mA
TJ Operating junction temperature −40 125 °C

6.4 Thermal Information

THERMAL METRIC(1) UCC28722 UNIT
DBV (SOT-23)
6 PINS
RθJA Junction-to-ambient thermal resistance 180.0 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 72.2 °C/W
RθJB Junction-to-board thermal resistance 44.4 °C/W
ψJT Junction-to-top characterization parameter 5.1 °C/W
ψJB Junction-to-board characterization parameter 43.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance NA °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

over operating free-air temperature range, VVDD = 25 V, HV = open, RCBC = open, TA = -40°C to 125°C, TA = TJ
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BIAS SUPPLY INPUT
IRUN Supply current, run IDRV = 0, run state 2.00 2.65 mA
IWAIT Supply current, wait IDRV = 0, wait state 95 170 µA
ISTART Supply current, start IDRV = 0, VVDD = 18 V, start state, IHV = 0 1.0 1.5 µA
IFAULT Supply current, fault IDRV = 0, fault state 2.00 2.65 mA
UNDERVOLTAGE LOCKOUT
VVDD(on) VDD turnon threshold VVDD low to high 19 21 23 V
VVDD(off) VDD turnoff threshold VVDD high to low 7.2 7.7 8.3 V
VS INPUT
VVSR Regulating level Measured at no-load condition, TJ = 25°C(1) 3.99 4.05 4.11 V
VVSNC Negative clamp level IVS = –300 µA, volts below ground 190 250 325 mV
IVSB Input bias current VVS = 4 V –0.25 0 0.25 µA
CS INPUT
VCST(max) Max CS threshold voltage VVS = 3.7 V 730 780 820 mV
VCST(min) Min CS threshold voltage VVS = 4.35 V 170 190 220 mV
KAM AM control ratio VCST(max) / VCST(min) 3.6 4.0 4.4 V/V
VCCR Constant current regulating level CC regulation constant 314 330 347 mV
KLC Line compensation current ratio IVSLS = –300 µA, IVSLS / current out of CS pin 24.0 25.0 28.6 A/A
TCSLEB Leading-edge blanking time DRV output duration, V CS = 1 V 230 290 355 ns
DRIVER
IDRS(max) Maximum DRV source current VDRV = 2 V, VVDD = 9 V, VVS = 3.85 V 31 37 42 mA
IDRS(min) Minimum DRV source current VDRV = 2 V, VVDD = 9 V, VVS = 4.30 V 15 19 23 mA
RDRVLS DRV low-side drive resistance IDRV = 10 mA 1 2.4 Ω
VDRCL DRV clamp voltage VVDD = 35 V 5.9 7 V
RDRVSS DRV pulldown in start state 20 25 kΩ
TIMING
fSW(max) Maximum switching frequency VVS = 3.7 V 72 80 89 kHz
fSW(min) Minimum switching frequency VVS = 4.35 V 570 650 750 Hz
tZTO Zero-crossing timeout delay 2.4 3.1 3.7 µs
PROTECTION
VOVP Overvoltage threshold At VS input, TJ = 25°C(1) 4.49 4.60 4.75 V
VOCP Overcurrent threshold At CS input 1.4 1.5 1.6 V
IVSL(run) VS line-sense run current Current out of VS pin increasing 188 225 277 µA
IVSL(stop) VS line-sense stop current Current out of VS pin decreasing 70 80 100 µA
KVSL VS line sense ratio IVSL(run) / IVSL(stop) 2.45 2.80 3.05 A/A
TJ(stop) Thermal shutdown temperature Internal junction temperature 165 °C
CABLE COMPENSATION
VCBC(max) Cable compensation maximum voltage Voltage at CBC at full load 2.9 3.1 3.5 V
VCVS(min) Minimum compensation at VS VCBC = open, change in VS regulating level at full load –55 –15 25 mV
VCVS(max) Maximum compensation at VS VCBC = 0 V, change in VS regulating level at full load 270 320 385 mV
(1) The regulating level and over voltage at VS decreases with temperature by 0.8 mV/˚C. This compensation is included to reduce the power supply output voltage variance over temperature.

6.6 Typical Characteristics

VDD = 25 V, unless otherwise noted.
UCC28722 SLUSB41_Figure 1.png
Figure 1. Bias Supply Current vs VDD Voltage
UCC28722 C003_SLUSBE8.png
Figure 3. VS Pin Regulation Voltage
vs Junction Temperature
UCC28722 C005_SLUSBE8.png
Figure 5. Current Sense Threshold
vs Temperature
UCC28722 C007_SLUSBE8.png
Figure 7. Minimum Switching Frequency
vs Junction Temperature
UCC28722 C008_SLUSBE8.png
Figure 9. Driver Output Source Current
vs Junction Temperature
UCC28722 C010_SLUSBE8.png
Figure 11. Over Voltage Protection Threshold
vs Junction Temperature
UCC28722 SLUSB41_Figure 2.png
Figure 2. Operating Current vs Junction Temperature
UCC28722 C004_SLUSBE8.png
Figure 4. VS Pin Start and Stop Thresholds
vs Junction Temperature
UCC28722 C006_SLUSBE8.png
Figure 6. Constant Current Regulation Level
vs Junction Temperature
UCC28722 C012_SLUSBE8.png
Figure 8. Maximum Switching Frequency
vs Junction Temperature
UCC28722 C009_SLUSBE8.png
Figure 10. Driver Pull Down Resistance
vs Junction Temperature