SLUSD71A April   2018  – May 2018 UCC28742

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Typical Efficiency of a 10-W, 5-V AC-to-DC Converter
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Detailed Pin Description
        1. 7.3.1.1 VDD (Device Bias Voltage Supply)
        2. 7.3.1.2 GND (Ground)
        3. 7.3.1.3 VS (Voltage-Sense)
        4. 7.3.1.4 DRV (Gate Drive)
        5. 7.3.1.5 CS (Current Sense)
        6. 7.3.1.6 FB (Feedback)
      2. 7.3.2 Secondary-Side Optically Coupled Constant-Voltage (CV) Regulation
      3. 7.3.3 Control Law
      4. 7.3.4 Constant Current Limit and Delayed Shutdown
      5. 7.3.5 Valley-Switching and Valley-Skipping
      6. 7.3.6 Start-Up Operation
      7. 7.3.7 Fault Protection
    4. 7.4 Device Functional Modes
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  VDD Capacitance, CDD
        3. 8.2.2.3  VDD Start-Up Resistance, RSTR
        4. 8.2.2.4  Input Bulk Capacitance and Minimum Bulk Voltage
        5. 8.2.2.5  Transformer Turns Ratio, Inductance, Primary-Peak Current
        6. 8.2.2.6  Transformer Parameter Verification
        7. 8.2.2.7  VS Resistor Divider and Line Compensation
        8. 8.2.2.8  Standby Power Estimate
        9. 8.2.2.9  Output Capacitance
        10. 8.2.2.10 Feedback Loop Design Consideration
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Custom Design With WEBENCH® Tools
      2. 11.1.2 Device Nomenclature
        1. 11.1.2.1  Capacitance Terms in Farads
        2. 11.1.2.2  Duty Cycle Terms
        3. 11.1.2.3  Frequency Terms in Hertz
        4. 11.1.2.4  Current Terms in Amperes
        5. 11.1.2.5  Current and Voltage Scaling Terms
        6. 11.1.2.6  Transformer Terms
        7. 11.1.2.7  Power Terms in Watts
        8. 11.1.2.8  Resistance Terms in Ω
        9. 11.1.2.9  Timing Terms in Seconds
        10. 11.1.2.10 Voltage Terms in Volts
        11. 11.1.2.11 AC Voltage Terms in VRMS
        12. 11.1.2.12 Efficiency Terms
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.3 Control Law

During voltage regulation (CV mode), the controller operates in frequency modulation mode and peak current amplitude modulation mode as illustrated in Figure 12 below. In CV mode operation, the control consists of four regions, namely, region FM 1, 2, AM and FM 3. The device internal VCL sets a particular region of operation. Refer to Figure 12 for VCL.

The device internally limits its operating frequency between fSW(min) and fSW(max), typically between 200 Hz and 105 kHz. The choice of transformer primary inductance and primary-peak current sets the maximum operating frequency of the converter, which must be equal to or lower than fSW(max). Conversely, the choice of maximum target operating frequency and primary-peak current determines the transformer primary-inductance value. The actual minimum switching frequency for any particular converter depends on several factors, including minimum loading level, leakage inductance losses, switch-node capacitance losses, other switching and conduction losses, and bias-supply requirements. In any case, the minimum steady-state frequency of the converter must always exceed fSW(min) or the output voltage may rise to the over-voltage protection level (OVP) and the controller responds as described in Fault Protection.

To achieve a regulated output voltage in the CV mode operation, energy balance has to be maintained. As the UCC28742 has a minimum switching frequency typical 200 Hz, together with the energy per switching cycle determined by converter parameters, such as the transformer primary inductance Lp and the selected RCS resistor, the converter has a minimum input power. A proper pre-load needs to be selected to ensure that this minimum energy is balanced during the no-load condition. The selection of the line compensation resistor value (RLC) connected to the CS pin can impact the energy per switching cycle based on low-line and high-line conditions. Typical Application section provides a design example to show how to implement these considerations.

UCC28742 UCC28742_control_law.gifFigure 12. Frequency and Amplitude Modulation Modes
(during CV mode)

The steady-state control-law voltage, VCL, ranges between 0.75 V to 4.90 V. Heavy load operation is usually in Region FM 3 where frequency modulation to output regulation is used and primary-peak current is controlled at its maximum. The AM region is usually for medium-load range typically from 10% load and above. In this region switching frequency is fixed at nominal 25 kHz along with primary-peak current varying from 25% to 100% of its maximum. The low operating frequency ranges are for lighter loads to achieve stable regulation at low frequencies. In regions FM 1 and 2, peak-primary current is always maintained at IPP(max)/4. Transitions between levels are automatically accomplished by the controller depending on the internal control-law voltage, VCL and its corresponding FB pin current IFB. An internal frequency-dithering mechanism is enabled in Region FM 3 to reduce conducted EMI, and is disabled otherwise. The Wait state is enabled in regions FM 1, 2, and AM, refer to Figure 11.