SLUSEW0 December   2023 UCC28750

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Detailed Pin Descriptions
      1. 7.3.1 VDD - Input Bias
      2. 7.3.2 DRV - Gate Drive Out
      3. 7.3.3 CS - Current Sensing
      4. 7.3.4 FB - Feedback
      5. 7.3.5 FLT - Fault
      6. 7.3.6 GND - Ground Return
    4. 7.4 Feature Description
      1. 7.4.1 Soft Start
      2. 7.4.2 Control Law
      3. 7.4.3 Frequency Dithering
      4. 7.4.4 Fault Protections
        1. 7.4.4.1 VDD Overvoltage and Undervoltage Lockout
        2. 7.4.4.2 Internal Overtemperature Protection
        3. 7.4.4.3 Output Overpower Protection
        4. 7.4.4.4 Output Short-Circuit Protection
        5. 7.4.4.5 FLT Pin Protections
      5. 7.4.5 Slope Compensation
    5. 7.5 Device Functional Modes
      1. 7.5.1 Off
      2. 7.5.2 Startup
      3. 7.5.3 On
      4. 7.5.4 Fault
      5. 7.5.5 Disabled
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Input Bulk Capacitance with Minimum Bulk Voltage
        2. 8.2.3.2 Transformer Turns Ratio and Inductance
        3. 8.2.3.3 Current Sense and Slope Compensation Network
        4. 8.2.3.4 Output Capacitors
        5. 8.2.3.5 VDD Capacitance, CVDD
      4. 8.2.4 Application Performance Plots
        1. 8.2.4.1 Startup
        2. 8.2.4.2 Load Transients
        3. 8.2.4.3 Q1 Drain Voltage Evaluation
      5. 8.2.5 What to Do and What Not to Do
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.3.3 Current Sense and Slope Compensation Network

The CS pin consists of a network of current sensing resistors and the slope compensation components. For designs with a maximum duty cycle less than 50%, the slope compensation network is not necessary, and thus the current sensing resistor is a calculation based on just the maximum peak current and the maximum threshold on the CS pin. The current sensing resistors connected from the source of the MOSFET to the ground control the maximum peak current of the power stage. The CS pin maximum threshold is 900mV, and a small margin is used to have a more robust design.

GUID-20230807-SS0I-HWH7-ZBJH-RKJKCG66QQKQ-low.svg Figure 8-2 CS Pin Diagram
Equation 16. R CS = 0.8 × V CS,max i pk

Because UCC28750 can operate in CCM and DCM, the boundary mode equation for ipk is used as a starting point for selecting the current sense resistor value, with RCS initially selected with a nominal value of 420mΩ.

Equation 17. I pk = V bulk,min × D max × T sw L

In a design with the duty cycle greater than 50% slope compensation must be used to avoid sub-harmonic isolation. UCC28750 has an internal ramp that helps remedy this issue. A resistor is added between the CS pin and the current sense resistor which programs the amount value of the ramp. In a peak-current current scheme, adding a ramp that is equal to half of the slope of the flyback transformer during the off-time of the switching device removes instability. The slope, Soff, with units Amps per second, and reflected to the primary side, during the off time of the primary switching MOSFET is shown in Equation 18.

Equation 18. S off = V o N P N S L

UCC28750 has a current source that ramps to 100μA at the device's maximum duty cycle of 80%. Therefore the ramp amplitude is a ratio of the max level and the calculated duty cycle of the design. The term islope has units of Amps per second, just like Soff.

Equation 19. i slope = i ramp D max × T sw

Where iramp is the 100μA amplitude of the slope compensation current during the fixed frequency (65/100 kHz) region in the control law.

The value of the Rslope resistor is half of the Soff value divided by the islope.

Equation 20. R slope = 1 2 × S off i slope

With a slope compensation resistor in place, the CS pin voltage needs to be re-evaluated to make sure that full power delivery is still possible at the minimum input voltage and highest load. The ramp that is generated from Rslope causes the CS pin threshold to be reached earlier than expected, if the RCS stays the same as calculated from Equation 16.

Equation 21. V CS,with slope comp = R slope × ( i slope × D max × T sw ) + R CS × I pk
Equation 22. V CS,with slope comp < 0.8 × V CS,max

VCS,with slope comp, the addition of the peak current, represented as a voltage, and the ramp from the slope compensation current source, can go above the threshold set in Equation 22. The slope compensation resistor is changed to be lowered, rather than the current sense changing to accommodate the value from Equation 20, as adding too much of a ramp can change the control mode from peak-current mode control to effectively voltage mode control.

Equation 21 is modified to solve for Rslope with RCS locked from the initial value of 420mΩ, the new Rslope is 1kΩ.