SLUS769D July   2013  – December 2016 UCC28910 , UCC28911


  1. Features
  2. Applications
  3. Description
  4. Simplified Schematic
  5. Revision History
  6. Device Comparison Table
  7. Pin Configuration and Functions
  8. Detailed Pin Description
    1. 8.1 VDD (Device Voltage Supply)
    2. 8.2 GND (Ground)
    3. 8.3 VS (Voltage Sense)
    4. 8.4 IPK (Set the Maximum DRAIN Current Peak)
    5. 8.5 DRAIN
  9. Specifications
    1. 9.1 Absolute Maximum Ratings
    2. 9.2 Storage Conditions
    3. 9.3 ESD Ratings
    4. 9.4 Recommended Operating Conditions
    5. 9.5 Thermal Information
    6. 9.6 Electrical Characteristics
    7. 9.7 Switching Characteristics
    8. 9.8 Typical Characteristics
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Primary-Side Voltage Regulation
      2. 10.3.2 Primary-Side Current Regulation
      3. 10.3.3 Voltage Feed Forward Compensation
      4. 10.3.4 Control Law
      5. 10.3.5 Valley Switching
      6. 10.3.6 Startup Operation
      7. 10.3.7 Fault Protection
        1. Output Over-Voltage
        2. Input Under-Voltage
        3. Primary Over-Current
        4. VDD Clamp Over-Current
        5. Thermal shutdown
      8. 10.3.8 EMI Dithering
    4. 10.4 Device Functional Modes
  11. 11Applications and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Battery Charger, 5 V, 6 W
        1. Design Requirements
        2. Detailed Design Procedure
          1.  Power Handling Curves
          2.  Input Stage Design and Bulk Capacitance
          3.  Transformer Turns Ratio
          4.  Output Capacitance
          5.  VDD Capacitance, CVDD
          6.  VS Resistor Divider
          7.  RVDD Resistor and Turn Ratio
          8.  Transformer Input Power
          9.  RIPK Value
          10. Transformer Primary Inductance Value
            1. Secondary Diode Selection
          11. Pre-Load
          12. DRAIN Voltage Clamp Circuit
      2. 11.2.2 Application Curves
        1. Average Efficiency Performance and Standby Power of the UCC28910FBEVM-526
      3. 11.2.3 Multi-Output Converter with UCC2891x Devices
      4. 11.2.4 Do’s and Don'ts
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Documentation Support
      1. 14.1.1 Device Nomenclature
        1. Definition of Terms
      2. 14.1.2 Related Documents
    2. 14.2 Trademarks
    3. 14.3 Electrostatic Discharge Caution
    4. 14.4 Glossary
    5. 14.5 Related Links
  15. 15Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Detailed Description


UCC28910 and UCC28911 are HV switchers dedicated to an off-line power supply in an isolated flyback configuration. HV switcher means that each device integrates the power switch, a 700-V power FET, with the control logic. The two devices have the same control logic and they are different only for the Power FET RDS(on) and for the operating current levels. The control logic controls both the output voltage and the output current without the need of an optical coupler. This control method is known as Primary-Side Regulation (PSR) and it operates by analyzing the voltage waveform on the auxiliary winding of the transformer. This allows significant cost saving with respect to traditional control scheme that uses an optical coupler for feedback from a secondary-side shunt regulator. The transformer auxiliary winding is also used to provide housekeeping supply power to the control logic. The device operates in Constant Voltage mode (CV) when it is controlling the output voltage. The device operates in Constant Current mode (CC) when the output current is controlled. The device operates in CV mode or in CC mode according to the load condition. (See Figure 24). A control algorithm that implements both modulation of the switching frequency and the amplitude modulation of the primary current peak, allows the power supply to operate efficiently over the entire load range. The high-voltage current source used for startup is kept off during normal operation thereby minimizing standby power consumption. The device also incorporates a smart power management to minimize its current consumption from the VDD pin. This power consumption is reduced when the converter is lightly loaded or unloaded allowing for a total input power of less than 30 mW when converter input voltage is 265 VAC and unloaded. A number of protection features inside the device allow for improved overall system reliability.

Functional Block Diagram

UCC28910 UCC28911 block_lus769.gif

Feature Description

UCC28911 and UCC28910 are flyback power supply switchers which provide accurate output voltage and constant current regulation with primary-side feedback, eliminating the need for optical coupler feedback circuits. The device has an internal 700-V power FET plus a controller which forces the converter to operate in discontinuous conduction mode with valley switching to minimize switching losses. The modulation scheme is a combination of frequency and primary-peak current modulation to provide optimized conversion efficiency over the entire load range. The control law provides a wide dynamic operating range to achieve less than 30-mW standby power.

UCC28911 and UCC28910 include features in the modulator to reduce the EMI peak energy of the fundamental switching frequency and harmonics. Accurate voltage and constant current regulation, fast dynamic response, and fault protection are achieved with primary-side control.

A complete charger solution can be realized with a straightforward design process, low cost and low component count solution.

Primary-Side Voltage Regulation

Figure 20 illustrates a flyback converter. The voltage regulation blocks of the device are shown. The power train operation is the same as any DCM flyback circuit but accurate output voltage and current sensing is the key to primary side control.

UCC28910 UCC28911 fig18_lus769.gif Figure 20. Voltage Loop Block Diagram

In primary-side control, the output voltage is sensed by the auxiliary winding during the transfer of transformer energy to the secondary. Figure 21 shows the down slope representing a decreasing total rectifier VF and the secondary winding resistance voltage drop as the secondary current decreases to 0 A. To achieve an accurate representation of the secondary output voltage on the auxiliary winding, the Discriminator Block (Figure 20) reliably ignores the leakage inductance reset and ring, continuously samples the auxiliary voltage during the down slope after the ringing is diminished, and captures the error signal at the time the secondary winding reaches 0 current. The internal reference on VS is 4.05 V (VVSR typical); the resistor divider is selected as outlined in the VS pin description.

UCC28910 UCC28911 fig19_lus769.gif Figure 21. Auxiliary Winding Voltage

The UCC28910 VS signal Discriminator Block (Figure 20) ensures accurate sampling time for an accurate sample of the output voltage from the auxiliary winding. There are however some details of the auxiliary winding signal to ensure reliable operation, specifically the reset time of the leakage inductance and the duration of any subsequent leakage inductance ring. Refer to Figure 22 for a detailed illustration of waveform criteria to ensure a reliable sample on the VS pin. The first detail to examine is the duration of the leakage inductance reset pedestal, tLK_RESET. Since this can mimic the waveform of the secondary current decay, followed by a sharp down-slope, it is important to keep the leakage reset time less than 500 ns for IDRAIN minimum, and less than 1.5 μs for IDRAIN maximum. The second detail is the amplitude of ringing on the auxiliary winding waveform (VAUX) following tLK_RESET. The peak-to-peak voltage at the VS pin should be less than approximately 100 mVp-p at least 200 ns before the end of the demagnetization time, tDMAG. If there is a concern with excessive ringing, it usually occurs during light or no-load conditions, when tDMAG is at the minimum. The tolerable ripple on VS is scaled up to the auxiliary winding voltage by RS1 and RS2, and is equal to 100 (RS1 + RS2) / RS2 mV.

During voltage regulation, the controller operates in frequency modulation mode and amplitude modulation mode. The internal operating frequency limits of the controller are 115 kHz maximum and 420 Hz minimum. The transformer primary inductance and turns ratio sets the maximum operating frequency of the converter. The output preload resistor and efficiency at low power determines the converter minimum operating frequency. There is no external compensation required for the UCC2891x devices.

UCC28910 UCC28911 fig20_lus769.gif Figure 22. VS Voltage

Primary-Side Current Regulation

Timing information at the VS pin and the primary current information allow accurate regulation of the secondary average current. The control law dictates that as power is increased in CV regulation and approaching CC regulation the primary-peak current is at ID_PK(max) = VCSTE(max) / RIPK. Referring to Figure 23, the primary-peak current, turns ratio, secondary demagnetization time (tDMAG), and switching period (tSW) establish the secondary average output current. When the average output current reaches the regulation reference in the current control block, the controller operates in frequency modulation mode to control the output current at any output voltage at or below the voltage regulation target as long as the aux winding can keep VDD above the VDD UVLO threshold (VDDOFF).

UCC28910 UCC28911 fig21_lus769.gif Figure 23. Output Current Estimation
UCC28910 UCC28911 fig22_lus769.gif Figure 24. Target Output V-I Characteristic

KCC is defined as the maximum value of the secondary-side conduction duty cycle (DMAGCC in Figure 23). It is set internally by the UCC2891x and occurs during constant current control mode.

UCC28910 UCC28911 fig23_lus769.gif Figure 25. Output Current Control Loop Block Diagram

Voltage Feed Forward Compensation

During normal operation the on-time is determined by sensing the power FET current and switching off the power FET as this current reaches a threshold fixed by the feedback loop according to the load condition. The power FET is not immediately turned off and its current, that is also the primary winding current, continues to rise for some time during the propagation delay (tDELAY in Figure 26). Keeping the reference for the PWM comparator constant, the value of the primary winding peak current depends on the slope of the primary winding current and tDELAY. The slope of the primary current is proportional to the flyback stage input voltage (VBULK)

UCC28910 UCC28911 fig24_lus769.gif Figure 26. Propagation Delay Effect on the Primary Current Peak
Equation 4. UCC28910 UCC28911 qu7_lus769.gif
Equation 5. UCC28910 UCC28911 qu8_lus769.gif

The current loop estimates the output current assuming the primary winding peak current is equal to the IPK_TARGET and compares this estimated current with a reference to obtain the current regulation. Considering, ID_PEAK is different from ID_PEAK_TARGET (see Figure 26) we need to compensate the effect of the propagation delay. The UCC28910 and the UCC28911 incorporate fully-integrated propagation-delay compensation that modifies the switching frequency keeping the output current constant during (CC) Constant Current Mode operation. This function is integrated in the controller and requires no external components. This feature keeps the output current constant despite input voltage variations and primary inductance value spread.

Control Law

During voltage regulation, the device operates in switching frequency modulation mode and primary current peak amplitude modulation mode. The internal operating frequency limits of the device are fSW(max) and fSW(min). During constant current regulation the device operates only in frequency modulation mode reducing the switching frequency as the output voltage decreases. Figure 27 shows how the primary peak current and the switching frequency change with respect to changes in load. The solid lines are primary-side peak current and the output voltage, the dotted lines are the switching frequency and output current.

UCC28910 UCC28911 fig25_lus769.gif Figure 27. Control Law Profile

Valley Switching

The UCC28910 and the UCC28911 utilize valley switching to reduce switching losses in the MOSFET and minimize the current spike at the FET turn on. The UCC28910 operates in valley switching in almost all load conditions until the VDS ringing is diminished. By switching at the lowest VDS voltage the MOSFET turn on dV / dt is minimized which is a benefit to reduce EMI.

Referring to Figure 28, devices will operate in a valley switching mode in most load conditions to switch-on at the lowest available VDS voltage. According to the load it is established a minimum switching period. The MOSFET is switched-on at the first valley that occurs after this minimum period is elapsed. With this control scheme the device can be turned-on at the first valley that occurs after transformer demagnetization or it can skip some valleys before turn-on operating in this case in the so called valley skipping mode. Valley switching is maintained during constant current regulation to provide improved efficiency and EMI benefits in constant current operation. If for some reason no valley is detected at the end of the tZTO time the MOSFET turns-on. In order to guarantee discontinuous mode operation at least the first valley needs to be detected or the Mosfet is not turned-on (see Figure 28).

UCC28910 UCC28911 fig26_lus769.gif Figure 28. Valley Skipping

In very light-load or no-load condition the VDS ringing amplitude is very low and not easy to detect, moreover with very low ringing amplitude there would be no benefit in valley switching so in this condition the valley switching is disabled (see Figure 29). The device switch on the MOSFET as soon the time tZTO is elapsed. The tZTO timer starts as soon as the minimum switching period is elapsed.

UCC28910 UCC28911 fig27_lus769.gif Figure 29. Valley Switching Disable at Light Load

Startup Operation

The UCC28910 and UCC28911 are provided with a high-voltage current source, connected between the DRAIN pin and the VDD pin; this current source is activated when a voltage is applied on DRAIN pin. The current source charges the capacitor connected between VDD and GND increasing the VDD voltage. As VDD exceeds VDDON the current source is turned off and the controller internal logic is activated and the device starts switching. If the VDD voltage falls below the VDDOFF threshold, or a fault condition is detected, the controller stops operation and its current consumption is reduced to ISTART or IFAULT. The high-voltage current source is turned on again when VDD voltage goes below VDDHV(on) (see Figure 30 for reference).

The initial three cycles are limited to ID_PEAK(max) / 3. This allows sensing any input or output faults with minimal power delivery. After the initial three cycles at ID_PEAK(max) / 3, the controller responds to the condition dictated by the control law.

UCC28910 UCC28911 fig28_lus769.gif Figure 30. Start Up and Auto Re-Start Operation

The converter remains in DCM during charging of the output capacitor(s), and operates in constant current mode until the output voltage is in regulation.

To avoid high-power dissipation inside the device, such as in the event that VDD is accidentally shorted to GND, the current provided by the high-voltage current source is reduced (ICH1) when VDD < 1 V (typical).

Fault Protection

There is comprehensive fault protection incorporated into the UCC2891x. Protection functions include:

  • Output Over-Voltage Fault
  • Input Under-Voltage Fault
  • Primary Over-Current Fault
  • VDD Clamp Over Current
  • Thermal Shut Down

Output Over-Voltage

The output over-voltage function is determined by the voltage feedback on the VS pin. If the voltage sample on VS exceeds 4.6 V, which correlates to 113.5% of nominal VOUT, the device stops switching and reduces its current consumption to IFAULT, slowly discharging the VDD capacitor to the VDDHV(on) threshold. At this time the standard startup sequence begins. The initial three cycles of startup at low-peak DRAIN current is important to monitor VOUT and deliver minimal power. The reset and restart, or hiccup, sequence applies for all fault protection. The slow VDD capacitor discharge after a fault allows the high voltage current source to have a low duty cycle to avoid over heating of the device if a fault condition is continuously present resulting in a repetitious start up sequence.

Input Under-Voltage

The input under voltage is determined by current information on the VS pin during the MOSFET on time. The VS pin is clamped close to GND during the MOSFET on time; at this time the current though RS1 is monitored to determine a sample of the bulk capacitor voltage. The under voltage shutdown current on VS is 75 μA; the enable current threshold is 210 μA. The device must sense the under-voltage condition for three consecutive switching cycles to recognize it as a fault condition. After an under-voltage fault, the same sequence described for output overvoltage occurs.

Primary Over-Current

The UCC28910 and the UCC28911 always operates with cycle-by-cycle primary current control. The normal operating range for the peak DRAIN current depends on the resistance (RIPK) connected between the IPK pin and the GND pin. The peak DRAIN current should not exceed ID_PEAK(max) even if the IPK pin is shorted to GND, or should not exceed VCSTE / RIPK if the IPK pin is tied to GND with the resistance RIPK. There are different reasons the DRAIN current can go out of control, for example a secondary winding short or hard saturation of the transformer. To avoid over-stress of the power FET additional protections are added. If the DRAIN current exceeds IDOCP (~33% higher than ID_PEAK(max)), such as when IPK pin is shorted to GND, or VCSTE_OCP / RIPK, (VCSTE_OCP ~33% higher than VCSTE(max)), and the condition is sensed for three consecutive switching cycles, a fault shutdown and retry sequence, detailed in the output overvoltage fault description, occurs. If the DRAIN current exceeds a second level of current (VCSTE_OCP2 / RIPK) it is not necessary to detect the fault for three consecutive switching cycles, the device will stop switching immediately.

VDD Clamp Over-Current

The VDD pin is provided with an internal clamp to prevent the pin voltage from exceeding the absolute maximum rating. If the current in the clamp exceeds 6 mA (typical), in order to avoid any damage to the device and to the system, a fault condition is assumed and the device stops operation.

Thermal shutdown

The internal thermal shutdown threshold is 150°C (typical) with a hysteresis of 50°C (typical). If an over-temperature is detected the device stops switching and its current consumption is reduced to IFAULT. The VDD voltage will decrease to VDDHV(on) where the high voltage current source is activated and the VDD voltage will rise again until VDD(on) where the internal logic is re-activated. If the temperature of the device is not dropped below approximately 100°C (150°C- 50°C) no switching cycles occurs and the fault condition is maintained and the current consumption is again IFAULT. For diagnostic purpose, when a thermal shut down occurs a short voltage pulse, whose amplitude is around 2 V, is transmitted on the IPK pin. Thermal shut down feature is not intended to protect the device itself but mainly to control the damage caused by the device thermally overstressed.

EMI Dithering

Generally, power supply designs need to pass EMI standard such as EN55022. When the device-controlled Flyback design is used as the auxiliary power supply in a larger system, such as motor drive or home appliance, the EMI filter for the entire system should be enough to filter out the EMI noise created by the Flyback converter. However, when the Flyback is a standalone power supply, the EMI noise becomes a concern.

The EMI noise is normally managed by adding necessary EMI filtering or circuit techniques such as the parasitic capacitor control, snubbering, or transformer EMI noise cancelation windings. Besides these, in both the UCC28910 and UCC28911 devices, the MOSFET switching speed is controlled so that the EMI noise can be minimized. Furthermore, EMI dithering technique is also implemented.

The EMI receiver uses a 9-kHz bandwidth detector to measure the noise energy within that bandwidth. If a power supply switching frequency is slightly changed with time, so that the switching frequency energy can be spread outside 9-kHz band, the measured EMI noise can be smaller. This technique makes it easier to pass the EMI standard. This switching frequency change technique is often called EMI dithering or jittering.

The EMI dithering scheme used in these devices effectively change the switching frequency outside of 9-kHz EMI receiver band, while minimize the output voltage ripple caused by the EMI dithering effect. The frequency modulation is based on a 12-cycle repeat rate. In each 12 switching cycles, there are three groups of 4 switching cycle, with three frequency deviations and three peak current settings. Figure 31 illustrates a group of 4 switching cycles, the center frequency and desired peak current. Figure 32 illustrates a group of reduced switching frequency (–7.5 kHz) with increased peak current (+3.5%) and a group of increased switching frequency (+7.5 kHz) with decreased peak current (–3.5%). The 7.5 kHz frequency deviation is selected to spread the switching frequency noise energy outside of 9-kHz EMI detector bandwidth. In turn, this frequency reduces the measured EMI noise.

UCC28910 UCC28911 emi_timing_cv_mode_slus769.gif Figure 31. EMI Dithering During CV Mode Operation
UCC28910 UCC28911 emi_timing_cc_mode_slus769.gif Figure 32. EMI Dithering During CC Mode Operation

The UCC28910 and UCC28911 devices control the Flyback converter during DCM operation only. The frequency change with fixed peak current may result in output voltage ripple because of the fluctuation of the energy delivery. By adjusting the peak current and frequency at the same time allows minimum variation on the energy delivery and reduces the output voltage ripple. During CC mode operation, the switching frequency is controlled to deliver the constant output current. Therefore, only the peak current is modulated to achieve equivalent EMI dithering.

The EMI dithering is disabled in the light load when the device enters a WAIT state.

Device Functional Modes

According to the input voltage, the VDD voltage, and the load conditions, the device can operate in different modes:

  1. At start-up with VDRAIN > 20 V, VDD = 0 V, the HV voltage current source is ON and starts to charge the capacitor connected to the VDD pin. With VDD < 1 V the current provided is limited < 500 µA and VDD rises slowly.
  2. When VDD exceeds 1 V (VDD < VDDON) the HV current source provides higher current and VDD rises faster.
  3. When VDD exceeds VDDON the device starts switching and delivers power to its output. According to its load, the converter operates in CV mode or in CC mode.
    1. CV mode means that the converter keeps the output voltage constant. This operating mode takes place when RLOAD > VOCV / IOCC where VOCV is the target for output voltage and IOCC is the maximum converter output current. In this condition the converter output voltage VOUT = VOCV and the converter output current IOUT < IOCC.
    2. CC mode means that the converter keeps the output current constant. This operating mode takes place when RLOAD < VOCV / IOCC. In this condition the converter output voltage VOUT < VOCV and the converter output current IOUT = IOCC.
  4. Device operations can be stopped because of the events listed below:
    1. If VDD drops below VDDOFF, the device stops switching and its current consumption is lowered to ISTART. Because the converter is not switching, no energy is delivered from the auxiliary winding, the HV current source is off, then the VDD capacitor is discharged with ISTART current.
    2. If a fault is detected device stops switching and its current consumption is lowered to IFAULT that slowly discharges the VDD capacitor down to VDDOFF where the current consumption is ISTART < IFAULT and the VDD capacitor continues to discharge.
  5. After the device stops switching, because of 4a or 4b, the VDD voltage drops, when it goes below VDDHV(on), the HV current source is turned on recharging the VDD capacitor up to VDDON.
  6. When a fault condition is permanently present, the device operates in auto restart-mode. This means that a fault condition is detected, the device stops operation as described in 4b, then VDD drops down to VDDHV(on) when the device start-up sequence takes place. At device turn-on, the fault is again detected and the cycle repeats.