SLUS458I July   2000  – June 2024 UCC28C40 , UCC28C41 , UCC28C42 , UCC28C43 , UCC28C44 , UCC28C45 , UCC38C40 , UCC38C41 , UCC38C42 , UCC38C43 , UCC38C44 , UCC38C45

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Detailed Pin Description
        1. 7.3.1.1 COMP
        2. 7.3.1.2 FB
        3. 7.3.1.3 CS
        4. 7.3.1.4 RT/CT
        5. 7.3.1.5 GND
        6. 7.3.1.6 OUT
        7. 7.3.1.7 VDD
        8. 7.3.1.8 VREF
      2. 7.3.2  Undervoltage Lockout
      3. 7.3.3  ±1% Internal Reference Voltage
      4. 7.3.4  Current Sense and Overcurrent Limit
      5. 7.3.5  Reduced-Discharge Current Variation
      6. 7.3.6  Oscillator Synchronization
      7. 7.3.7  Soft-Start Timing
      8. 7.3.8  Enable and Disable
      9. 7.3.9  Slope Compensation
      10. 7.3.10 Voltage Mode
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 UVLO Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Input Bulk Capacitor and Minimum Bulk Voltage
        2. 8.2.2.2  Transformer Turns Ratio and Maximum Duty Cycle
        3. 8.2.2.3  Transformer Inductance and Peak Currents
        4. 8.2.2.4  Output Capacitor
        5. 8.2.2.5  Current Sensing Network
        6. 8.2.2.6  Gate Drive Resistor
        7. 8.2.2.7  VREF Capacitor
        8. 8.2.2.8  RT/CT
        9. 8.2.2.9  Start-Up Circuit
        10. 8.2.2.10 Voltage Feedback Compensation
          1. 8.2.2.10.1 Power Stage Poles and Zeroes
          2. 8.2.2.10.2 Slope Compensation
          3. 8.2.2.10.3 Open-Loop Gain
          4. 8.2.2.10.4 Compensation Loop
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Precautions
        2. 8.4.1.2 Feedback Traces
        3. 8.4.1.3 Bypass Capacitors
        4. 8.4.1.4 Compensation Components
        5. 8.4.1.5 Traces and Ground Planes
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
  • DGK|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

VVDD = 15V (1), RRT = 10kΩ, CCT = 3.3nF, CVDD = 0.1µF and no load on the outputs, TJ = –40°C to 125°C for the UCC28C4x and TJ = 0°C to 85°C for the UCC38C4x (unless otherwise noted).
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
REFERENCE
VVREFVREF voltage, initial accuracyTJ = 25°C, IOUT = 1mA4.955.1V
Line regulationVVDD = 12V to 18V0.220mV
Load regulation1mA to 20mA325mV
Temperature stabilitySee (2)0.20.4mV/°C
Total output variationSee (2)4.825.18V
VREF noise voltage10Hz to 10kHz, TJ = 25°C, see (2)50µV
Long term stability1000 hours, TJ = 125°C, see (2)525mV
IVREFOutput short circuit (source current)304555mA
OSCILLATOR
fOSCInitial accuracyTJ = 25°C, see (3)50.55355kHz
Voltage stability12V ≤ VVDD ≤18V0.2%1%
Temperature stabilityTJ(MIN) to TJ(MAX), see (2)1%2.5%
AmplitudeRT/CT pin peak-to-peak voltage1.9V
Discharge currentTJ = 25°C, VRT/CT = 2V, see (4)7.78.49mA
VRT/CT = 2V, see (4)7.28.49.5
ERROR AMPLIFIER
VFBFeedback input voltage, initial accuracyVCOMP = 2.5V, TJ = 25°C2.4752.52.525V
Feedback input voltage, total variationVCOMP = 2.5V2.452.52.55V
IFBInput bias current (source current)VFB = 5V0.12µA
AVOLOpen-loop voltage gain2V ≤ VOUT ≤ 4V6590dB
Unity gain bandwidthSee (2)11.5MHz
PSRRPower supply rejection ratio12V ≤ VVDD ≤ 18V60dB
Output sink currentVFB = 2.7V, VCOMP = 1.1V214mA
Output source currentVFB = 2.3V, VCOMP = 5V0.51mA

Output source current(2)

VFB ≤ 2.3V, VCOMP = 0V5.5mA
VOHHigh-level COMP voltageVFB = 2.3V, RCOMP = 15kΩ COMP to GND

VREF - 0.2

V
VOLLow-level COMP voltageVFB = 2.7V, RCOMP = 15kΩ COMP to VREF0.11.1V
CURRENT SENSE
ACSGainSee (5)(6)2.8533.15V/V
VCSMaximum input signalVFB < 2.4V0.911.1V
PSRRPower supply rejection ratioVVDD = 12V to 18V(2)(5)70dB
ICSInput bias current (source current)0.12µA
tDCS to output delay3570ns
COMP to CS offsetVCS = 0V1.15V
OUTPUT
VOUT(low)RDS(on) pulldownISINK = 200mA5.515Ω
VOUT(high)RDS(on) pullupISOURCE = 200mA1025Ω
tRISERise tImeTJ = 25°C, COUT = 1nF2550ns
tFALLFall tImeTJ = 25°C, COUT = 1nF2040ns
UNDERVOLTAGE LOCKOUT
VDDONStart thresholdUCCx8C42, UCCx8C4413.514.515.5V
UCCx8C43, UCCx8C457.88.49
UCCx8C40, UCCx8C416.577.5
VDDOFFMinimum operating voltageUCCx8C42, UCCx8C448910V
UCCx8C43, UCCx8C4577.68.2
UCCx8C40, UCCx8C416.16.67.1
PWM
DMAXMaximum duty cycleUCCx8C42, UCCx8C43, UCCx8C40, VFB < 2.4 V94%96%
UCCx8C44, UCCx8C45, UCCx8C41, VFB < 2.4 V47%48%
DMINMinimum duty cycleVFB > 2.6V0%
CURRENT SUPPLY
ISTART-UPStart-up currentVVDD = VDDON – 0.5V50100µA
IVDDOperating supply currentVFB = VCS = 0V2.33mA
(1) Adjust VVDD above the start threshold before setting at and 15.5V.
(2) Specified by design. Not production tested.
(3) Output frequencies of the UCCx8C41, UCCx8C44, and the UCCx8C45 are half the oscillator frequency.
(4) Oscillator discharge current is measured with RRT = 10kΩ to VREF.
(5) Parameter measured at trip point of latch with VFB = 0V.
(6) Gain is defined as ACS = ΔVCOMP / ΔVCS , 0V ≤ VCS ≤ 900mV