SLUSFP1B April   2025  – November 2025 UCC34141-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Insulation Specifications
    6. 6.6 Electrical Characteristics
    7. 6.7 Safety-Related Certifications
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Stage Operation
        1. 7.3.1.1 VDD-COM Voltage Regulation
        2. 7.3.1.2 COM-VEE Voltage Regulation
        3. 7.3.1.3 COM-VEE Output Capability
      2. 7.3.2 Output Voltage Soft Start
      3. 7.3.3 ENA and Power-Good
      4. 7.3.4 Protection Functions
        1. 7.3.4.1 Input Undervoltage Lockout
        2. 7.3.4.2 Input Overvoltage Lockout
        3. 7.3.4.3 Output Undervoltage Protection
        4. 7.3.4.4 Output Overvoltage Protection
        5. 7.3.4.5 Over-Temperature Protection
        6. 7.3.4.6 BSW Pin Faults Protection
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 VDD-COM Voltage Regulation
        2. 8.2.2.2 COM-VEE Voltage Regulation and Single Output Configuration
    3. 8.3 System Examples
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Third-Party Products Disclaimer
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information
    2. 11.2 Tape and Reel Information
    3. 11.3 Mechanical Data

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DHA|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions


UCC34141-Q1 DHA Package, 16-Pin SSOP (Top View)

Figure 5-1 DHA Package, 16-Pin SSOP (Top View)
Table 5-1 Pin Functions
PIN TYPE (1) DESCRIPTION
NAME NO.
ENA 1

I

 Enable pin. Forcing ENA LOW disables the device. Pull HIGH to enable normal device functionality. 5.5V recommended maximum. Can be used to program input UVLO with a resistor divider from VIN.
PG(PG) 2 O

Power-Good open-drain output pin. Remains active when VVIN_UVLOP ≤ VVIN ≤ VVIN_OVLOP; VVDD_UVP ≤ VFBVDD ≤ VVDD_OVP; VVEE_UVP ≤ VFBVEE ≤ VVEE_OVP; TJ_Primary ≤ TSHUT_P_R; and TJ_secondary ≤ TSHUT_S_R. Connect a decoupling capacitor in 0402 body size for by-passing the high frequency noise. It must be next to the Power-Good pin on the same side of the PCB as the IC.
VIN 3, 4 P

Primary input voltage. Connect a 10µF and a parallel 0.1µF ceramic capacitor from VIN to GNDP. The 0.1µF ceramic capacitor in 0402 body size is for by-passing the high frequency noise and must be next to the VIN and GNDP pins on the same side of the PCB as the IC.
GNDP 5, 6, 7, 8 G Primary-side ground connection for VIN. Place several vias to copper pours for thermal relief.

See the "Layout" section for more details.
COMA 9 G

Secondary-side analog sense reference connection for the noise sensitive analog feedback input FBVDD, and FBVEE. Connect the low-side FBVDD feedback resistor and high frequency decoupling filter capacitors close to the COMA pin and respective feedback pin FBVDD. Connect to secondary-side gate drive voltage reference, COM. Use a single point connection and place the high frequency decoupling ceramic capacitor close to the COMA pin.

COM

 10, 11 G Secondary ground. Connect to Source of power switch.
VDD 12 P Secondary-side isolated output voltage from transformer. Connect a 10µF and a parallel 0.1µF ceramic capacitor from VDD to COM. The 0.1µF ceramic capacitor in 0402 body size is for bypassing high frequency noise and must be next to the VDD and COM pins.
BSW 13 P Internal buck-boost converter switch pin. Connect an inductor from this pin to COM. Recommend a 3.3µH to 10µH chip inductor.
VEE 14 P Secondary-side isolated output voltage for negative rail. Connect a 2.2µF ceramic capacitor from VEE to COM for bypassing high frequency noise.
FBVDD 15 I Feedback (VDD – COM) output voltage sense pin and to adjust the output (VDD – COM) voltage. Connect a resistor divider from VDD to COMA so that the midpoint is connected to FBVDD. The equivalent FBVDD voltage is regulated at 2.5V with the internal hysteresis control across isolation. Adding a 220pF ceramic capacitor for high frequency decoupling in parallel with the low-side feedback resistor is needed. The 220pF ceramic capacitor for high frequency bypass must be next to the FBVDD and COMA pins on top layer or back layer connected with vias.
FBVEE 16 I Feedback (COM – VEE) output voltage sense pin used to adjust the output (COM – VEE) voltage. Connect one feedback resistor to VEE to program the (COM – VEE) voltage from 2V to 8V. Connect a 10pF ceramic capacitor from FBVEE to COMA for bypassing high frequency noise. The 10pF ceramic capacitor must be next to the FBVEE pin on top layer or back layer connected with vias.
(1) P = power, G = ground, I = input, O = output