SLUS504H SEPTEMBER   2002  – January 2016 UCC27321 , UCC27322 , UCC37321 , UCC37322


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Power Dissipation Ratings
    8. 7.8 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Stage
      2. 8.3.2 Output Stage
      3. 8.3.3 Source and Sink Capabilities during Miller Plateau
      4. 8.3.4 Enable
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. Input-to-Output Configuration
        2. Input Threshold Type
        3. VDD Bias Supply Voltage
        4. Peak Source and Sink Currents
        5. Enable and Disable Function
        6. Propagation Delay
        7. Power Dissipation
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Information
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Related Products
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
  • P|8
  • DGN|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Application and Implementation


Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

High-current gate driver devices are required in switching power applications for a variety of reasons. To enable fast switching of power devices and reduce associated power losses, a powerful gate driver can be employed between the PWM output of controllers or signal isolation devices and the gates of the power semiconductor devices. Further, gate drivers are indispensable when sometimes it is just not feasible to have the PWM controller directly drive the gates of the switching devices. The situation may be encountered because the PWM signal from a digital controller or signal isolation device is often a 3.3-V or 5-V logic signal which is not capable of effectively turning on a power switch. A level-shifting circuitry is needed to boost the logic-level signal to the gate-drive voltage to fully turn on the power device and minimize conduction losses. Traditional buffer drive circuits based on NPN/PNP bipolar, (or P- N- channel MOSFET), transistors in totem-pole arrangement, being emitter follower configurations, prove inadequate for this because they lack level-shifting capability and low-drive voltage protection. Gate drivers effectively combine both the level-shifting and buffer drive functions. Gate drivers may also minimize the effect of switching noise by locating the high-current driver physically close to the power switch, drive gate-driver transformers and control floating power device gates, reducing power dissipation and thermal stress in controllers by absorbing gate-charge power losses.

In summary gate drivers are extremely important components in switching power combining benefits of high-performance, low-cost, low component count, board-space reduction, and simplified system design.

9.2 Typical Application

UCC27321 UCC27322 UCC37321 UCC37322 typ_app_slus504.gif Figure 27. Typical Application Diagram of UCC27322 and UCC37322

9.2.1 Design Requirements

When selecting the proper gate driver device for an end application, some design considerations must be evaluated first to make the most appropriate selection. The following design parameters should be used when selecting the proper gate driver device for an end application: input-to-output configuration, the input threshold type, bias supply voltage levels, peak source and sink currents, availability of independent enable and disable functions, propagation delay, power dissipation, and package type. See the example design parameters and requirements in Table 2.

Table 2. Design Parameters

Input-to-output configuration Noninverting
Input threshold type CMOS
Bias supply voltage levels 12 V
dVDS/dt(1) 20 V/ns
Enable function Yes
Propagation delay < 50 ns
Power dissipation < 0.45 W
Package type SOIC (8)
(1) dVDS/dt is a typical requirement for a given design. This value can be used to find the peak source/sink currents needed as shown in Peak Source and Sink Currents.

9.2.2 Detailed Design Procedure Input-to-Output Configuration

The design should specify which type of input-to-out configuration should be used. If turning on the power MOSFET or IGBT when the input signal is in high state is preferred, then a device capable of the noninverting configuration must be selected. If turning off the power MOSFET or IGBT when the input signal is in high state is preferred, then a device capable of the inverting configuration must be chosen. Based on this noninverting requirement of this application, the proper device out of the UCC27322 or UCC37322 should be selected. Input Threshold Type

The type of input voltage threshold determines the type of controller that can be used with the gate driver device. The UCC2732x and UCC3732x devices feature a TTL and CMOS-compatible input threshold logic, with wide hysteresis. The threshold voltage levels are low voltage and independent of the VDD supply voltage, which allows compatibility with both logic-level input signals from microcontrollers as well as higher-voltage input signals from analog controllers. See Electrical Characteristics for the actual input threshold voltage levels and hysteresis specifications for the UCC2732x and UCC3732x devices. VDD Bias Supply Voltage

The bias supply voltage to be applied to the VDD pins of the device must never exceed the values listed in Recommended Operating Conditions. However, different power switches require different voltage levels to be applied at the gate. With a wide operating range from 4.5 V to 15 V, the UCC2732x and UCC3732x can be used to drive a variety of power switches, such as Si MOSFETs (for example, Vgs = 4.5 V, 10 V, 12 V), IGBTs (VGE=15 V), and wide-bandgap power semiconductors (such as GaN, certain types of which allow no higher than 6 V to be applied to the gate terminals). Peak Source and Sink Currents

Generally, the switching speed of the power switch during turnon and turnoff must be as fast as possible to minimize switching power losses. The gate driver device must be able to provide the required peak current for achieving the targeted switching speeds for the targeted power MOSFET.

Using the example of a power MOSFET, the system requirement for the switching speed is typically described in terms of the slew rate of the drain-to-source voltage of the power MOSFET (such as dvDS/dt). For example, the system requirement might state that a SPP20N60C3 power MOSFET must be turned on with a Dvds/dt of 20 V/ns or higher under a DC bus voltage of 400 V in a continuous-conduction-mode (CCM) boost PFC-converter application. This type of application is an inductive hard-switching application and reducing switching power loss is critical. This requirement means that the entire drain-to-source voltage swing during power MOSFET turnon event (from 400 V in the OFF state to VDS(on) in ON state) must be completed in approximately 20 ns or less. When the drain-to-source voltage swing occurs, the Miller charge of the power MOSFET (Qgd parameter in SPP20N60C3 power MOSFET data sheet is 33 nC typically) is supplied by the peak current of gate driver. According to power MOSFET inductive switching mechanism, the gate-to-source voltage of the power MOSFET at this time is the Miller plateau voltage, which is typically a few volts higher than the threshold voltage of the power MOSFET, VGS(th)).

To achieve the targeted Dvds/dt, the gate driver must be capable of providing the Qgd charge in 20 ns or less. In other words, a peak current of 1.65 A (= 33 nC) / 20 ns) or higher must be provided by the gate driver. The UCC2732x and UCC3732x devices can provide 9-A peak sourcing/sinking current which clearly exceeds the design requirement and has the capability to meet the switching speed needed. This 9-A peak sourcing/sinking current provides an extra margin against part-to-part variations in the Qgd parameter of the power MOSFET along with additional flexibility to insert external gate resistors and fine tune the switching speed for efficiency versus EMI optimizations. However, in practical designs the parasitic trace in the gate driver circuit of the PCB will have a definitive role to play on the power MOSFET switching speed. The effort of this trace inductance is to limit the di/dt of the output current pulse of the gate driver. To illustrate this effect, consider output current pulse waveform from the gate driver to be approximated to a triangular profile, where the area under the triangle (0.5 × IPEAK × time) would equal the total gate charge of the power MOSFET (Qg parameter in SPP20N60C3 power MOSFET data sheet= 87 nC typically). If the parasitic trace inductance limits the di/dt then a situation may occur in which the full peak current capability of the gate driver is not fully achieved in the time required to deliver the Qg required for the power MOSFET switching. In other words, the time parameter in the equation would dominate and the IPEAK value of the current pulse would be much less than the true peak current capability of the device, while the required Qg is still delivered. Because of this, the desired switching speed may not be realized, even when theoretical calculations indicate the gate driver can achieve the targeted witching speed. Thus, placing the gate driver device very close to the power MOSFET and designing a tight gate drive-loop with minimal PCB trace inductance is important to realize the full peak-current capability of the gate driver. Enable and Disable Function

Certain applications demand independent control of the output state of the driver without involving the input signal. A pin which offers enable and disable functions achieves the requirements. For these applications, the UCC2732x and UCC3732x are suitable as they feature an input pin and an Enable pin. Propagation Delay

The acceptable propagation delay from the gate driver is dependent on the switching frequency at which it is used and the acceptable level of pulse distortion to the system. The UCC2732x and UCC3732x devices feature 25-ns turnon propagation delay and 35-ns turnoff propagation delay (typical), which ensure very little distortion and allow operation at higher frequencies. See Electrical Characteristics for the propagation and Switching Characteristics of the UCC2732x and UCC3732x devices. Power Dissipation

The UCC3732x family of drivers are capable of delivering 9-A of current to a MOSFET gate for a period of several hundred nanoseconds. High peak current is required to turn an N-channel device ON quickly. Then, to turn the device OFF, the driver is required to sink a similar amount of current to ground. This repeats at the operating frequency of the power device. An N-channel MOSFET is used in this discussion because it is the most common type of switching device used in high-frequency power conversion equipment.

References (1) and (2) contain detailed discussions of the drive current required to drive a power MOSFET and other capacitive-input switching devices. Much information is provided in tabular form to give a range of the current required for various devices at various frequencies. The information pertinent to calculating gate drive current requirements will be summarized here; the original document is available from the TI website.

When a driver device is tested with a discrete, capacitive load it is a fairly simple matter to calculate the power that is required from the bias supply. The energy that must be transferred from the bias supply to charge the capacitor is given by Equation 1.

Equation 1. UCC27321 UCC27322 UCC37321 UCC37322 equation1_lus504.gif


  • C is the load capacitor
  • V is the bias voltage feeding the driver

There is an equal amount of energy transferred to ground when the capacitor is discharged. This leads to a power loss given by Equation 2.

Equation 2. UCC27321 UCC27322 UCC37321 UCC37322 equation2_lus504.gif


  • f is the switching frequency

This power is dissipated in the resistive elements of the circuit. Thus, with no external resistor between the driver and gate, this power is dissipated inside the driver. Half of the total power is dissipated when the capacitor is charged, and the other half is dissipated when the capacitor is discharged. An example using the conditions of the previous gate-drive waveform should help clarify this.

With VDD = 12 V, CLOAD = 10 nF, and f = 300 kHz, the power loss can be calculated as shown in Equation 4.

Equation 3. P = 10 nF × (12)2 × (300 kHz) = 0.432 W

With a 12-V supply, this would equate, as shown in Equation 4, to a current of:

Equation 4. UCC27321 UCC27322 UCC37321 UCC37322 equation3_lus504.gif

The switching load presented by a power MOSFETcan be converted to an equivalent capacitance by examining the gate charge required to switch the device. This gate charge includes the effects of the input capacitance plus the added charge needed to swing the drain of the device between the ON and OFF states. Most manufacturers provide specifications that provide the typical and maximum gate charge, in nC, to switch the device under specified conditions. Using the gate charge Qg, one can determine the power that must be dissipated when charging a capacitor. This is done by using the equivalence Qg = CeffV to provide Equation 5 for power.

Equation 5. P = C × V2 × f = Qg × V × f

Equation 5 allows a power designer to calculate the bias power required to drive a specific MOSFET gate at a specific bias voltage.

9.2.3 Application Curves

UCC27321 UCC27322 UCC37321 UCC37322 typ_fig25_lus504.gif
Figure 28. Output Behavior vs VDD (UCC37322)
UCC27321 UCC27322 UCC37321 UCC37322 typ_fig26_lus504.gif
Figure 29. Output Behavior vs VDD (UCC37322)