SLUSFA7 July   2025 UCC57142 , UCC57148

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Pin Configuration and Functions
  6. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Timing Diagram
    8. 5.8 Typical Characteristics
  7. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Stage
      2. 6.3.2 Enable/Fault (EN/FLT)
      3. 6.3.3 Driver Stage
      4. 6.3.4 Over Current (OC) Protection
      5. 6.3.5 Thermal Shutdown
    4. 6.4 Device Functional Modes
  8. 7 Applications and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Driving MOSFET/IGBT/SiC MOSFET
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 VDD Undervoltage Lockout
          2. 7.2.1.2.2 Power Dissipation
        3. 7.2.1.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
      3. 7.4.3 Thermal Consideration
  9. 8Revision History
  10. 9Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DBV|6
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.3 Driver Stage

The device has a ±3-A peak drive strength and is suitable for driving Si MOSFET/ IGBT/SiC. The driver features an important safety function wherein, when the input pins are in a floating condition, the output is held in the LOW state. The driver has rail-to-rail output by implementing an NMOS pullup with intrinsic bootstrap gate drive. Under DC conditions, a PMOS is used to keep OUT tied to VDD as shown in the following figure. The low pullup impedance of the NMOS results in strong drive strength during the turn-on transient, which shortens the charging time of the input capacitance of the power semiconductor and reduces the turn on switching loss.

UCC57142 UCC57148 Gate Driver Output Stage Figure 6-2 Gate Driver Output Stage