SLVSAC8D November   2010  – April  2019 UCD90160

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified Application Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements: I2C/SMBus/PMBus
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Rail Configuration
      2. 7.3.2 TI Fusion GUI
      3. 7.3.3 PMBus Interface
    4. 7.4 Device Functional Modes
      1. 7.4.1  Power-Supply Sequencing
        1. 7.4.1.1 Turn-on Sequencing
        2. 7.4.1.2 Turn-off Sequencing
        3. 7.4.1.3 Sequencing Configuration Options
      2. 7.4.2  Pin-Selected Rail States
      3. 7.4.3  Voltage Monitoring
      4. 7.4.4  Fault Responses and Alert Processing
      5. 7.4.5  Shut Down All Rails and Sequence On (Resequence)
      6. 7.4.6  GPIOs
      7. 7.4.7  GPO Control
      8. 7.4.8  GPO Dependencies
        1. 7.4.8.1 GPO Delays
        2. 7.4.8.2 State Machine Mode Enable
      9. 7.4.9  GPI Special Functions
      10. 7.4.10 Power-Supply Enables
      11. 7.4.11 Cascading Multiple Devices
      12. 7.4.12 PWM Outputs
        1. 7.4.12.1 FPWM1-8
        2. 7.4.12.2 PWM1-4
      13. 7.4.13 Programmable Multiphase PWMs
      14. 7.4.14 Margining
        1. 7.4.14.1 Open-Loop Margining
        2. 7.4.14.2 Closed-Loop Margining
      15. 7.4.15 System Reset Signal
      16. 7.4.16 Watch Dog Timer
      17. 7.4.17 Run Time Clock
      18. 7.4.18 Data and Error Logging to Flash Memory
      19. 7.4.19 Brownout Function
      20. 7.4.20 PMBus Address Selection
    5. 7.5 Programming
      1. 7.5.1 Device Configuration and Programming
        1. 7.5.1.1 Full Configuration Update While in Normal Mode
      2. 7.5.2 JTAG Interface
      3. 7.5.3 Internal Fault Management and Memory Error Correction (ECC)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
      4. 8.2.4 Estimating ADC Reporting Accuracy
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.12.1 FPWM1-8

Pins 17–24 can be configured as fast pulse-width modulators (FPWMs). The frequency range is 15.260 kHz to 125 MHz. FPWMs can be configured as closed-loop margining outputs, fan controllers or general-purpose PWMs.

Any FPWM pin not used as a PWM output can be configured as a GPIO. One FPWM in a pair can be used as a PWM output and the other pin can be used as a GPO. The FPWM pins are actively driven low from reset when used as GPOs.

The frequency settings for the FPWMs apply to pairs of pins:

  • FPWM1 and FPWM2 – same frequency
  • FPWM3 and FPWM4 – same frequency
  • FPWM5 and FPWM6 – same frequency
  • FPWM7 and FPWM8 – same frequency

If an FPWM pin from a pair is not used while its companion is set up to function as a PWM, it is recommended to configure the unused FPWM pin as an active-low open-drain GPO so that it does not disturb the rest of the system. By setting an FPWM, it automatically enables the other FPWM within the pair if it was not configured for any other functionality.

The frequency for the FPWM is derived by dividing down a 250MHz clock. To determine the actual frequency to which an FPWM can be set, must divide 250MHz by any integer between 2 and (214-1).

The FPWM duty cycle resolution is dependent on the frequency set for a given FPWM. Once the frequency is known the duty cycle resolution can be calculated as Equation 1.

Equation 1. Change per Step (%)FPWM = frequency ÷ (250 × 106 × 16)

Take for an example determining the actual frequency and the duty cycle resolution for a 75MHz target frequency.

  1. Divide 250MHz by 75MHz to obtain 3.33.
  2. Round off 3.33 to obtain an integer of 3.
  3. Divide 250MHz by 3 to obtain actual closest frequency of 83.333MHz.
  4. Use Equation 1 to determine duty cycle resolution to obtain 2.0833% duty cycle resolution.