SNLS614B
September 2018 – December 2022
DP83869HM
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Description (continued)
6
Device Comparison Table
7
Pin Configuration and Functions
8
Specifications
8.1
Absolute Maximum Ratings
8.2
ESD Ratings
8.3
Recommended Operating Conditions
8.4
Thermal Information
8.5
Electrical Characteristics
8.6
Timing Requirements
8.7
Timing Diagrams
8.8
Typical Characteristics
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.3
Feature Description
9.3.1
WoL (Wake-on-LAN) Packet Detection
9.3.1.1
Magic Packet Structure
9.3.1.2
Magic Packet Example
9.3.1.3
Wake-on-LAN Configuration and Status
9.3.2
Start of Frame Detect for IEEE 1588 Time Stamp
9.3.2.1
SFD Latency Variation and Determinism
9.3.2.1.1
1000-Mb SFD Variation in Master Mode
9.3.2.1.2
1000-Mb SFD Variation in Slave Mode
9.3.2.1.3
100-Mb SFD Variation
9.3.3
Clock Output
9.3.4
Loopback Mode
9.3.4.1
Near-End Loopback
9.3.4.1.1
MII Loopback
9.3.4.1.2
PCS Loopback
9.3.4.1.3
Digital Loopback
9.3.4.1.4
Analog Loopback
9.3.4.1.5
External Loopback
9.3.4.1.6
Far-End (Reverse) Loopback
39
9.3.5
BIST Configuration
9.3.6
Interrupt
9.3.7
Power-Saving Modes
9.3.7.1
IEEE Power Down
9.3.7.2
Active Sleep
9.3.7.3
Passive Sleep
9.3.8
Mirror Mode
9.3.9
Speed Optimization
9.3.10
Cable Diagnostics
9.3.10.1
TDR
9.3.11
Fast Link Drop
9.3.12
Jumbo Frames
9.4
Device Functional Modes
9.4.1
Copper Ethernet
9.4.1.1
1000BASE-T
9.4.1.2
100BASE-TX
9.4.1.3
10BASE-Te
9.4.2
Fiber Ethernet
9.4.2.1
1000BASE-X
9.4.2.2
100BASE-FX
9.4.3
Serial GMII (SGMII)
9.4.4
Reduced GMII (RGMII)
9.4.4.1
1000-Mbps Mode Operation
9.4.4.2
1000-Mbps Mode Timing
9.4.4.3
10- and 100-Mbps Mode
9.4.5
Media Independent Interface (MII)
9.4.6
Bridge Modes
9.4.6.1
RGMII-to-SGMII Mode
9.4.6.2
SGMII-to-RGMII Mode
69
9.4.7
Media Convertor Mode
9.4.8
Register Configuration for Operational Modes
9.4.8.1
RGMII-to-Copper Ethernet Mode
9.4.8.2
RGMII-to-1000Base-X Mode
9.4.8.3
RGMII-to-100Base-FX Mode
9.4.8.4
RGMII-to-SGMII Bridge Mode
9.4.8.5
1000M Media Convertor Mode
9.4.8.6
100M Media Convertor Mode
9.4.8.7
SGMII-to-Copper Ethernet Mode
9.4.9
Serial Management Interface
9.4.9.1
Extended Address Space Access
9.4.9.1.1
Write Address Operation
9.4.9.1.2
Read Address Operation
9.4.9.1.3
Write (No Post Increment) Operation
9.4.9.1.4
Read (No Post Increment) Operation
9.4.9.1.5
Write (Post Increment) Operation
9.4.9.1.6
Read (Post Increment) Operation
9.4.9.1.7
Example of Read Operation Using Indirect Register Access
9.4.9.1.8
Example of Write Operation Using Indirect Register Access
9.4.10
Auto-Negotiation
9.4.10.1
Speed and Duplex Selection - Priority Resolution
9.4.10.2
Master and Slave Resolution
9.4.10.3
Pause and Asymmetrical Pause Resolution
9.4.10.4
Next Page Support
9.4.10.5
Parallel Detection
9.4.10.6
Restart Auto-Negotiation
9.4.10.7
Enabling Auto-Negotiation Through Software
9.4.10.8
Auto-Negotiation Complete Time
9.4.10.9
Auto-MDIX Resolution
9.5
Programming
9.5.1
Strap Configuration
9.5.1.1
Straps for PHY Address
9.5.1.2
Strap for DP83869HM Functional Mode Selection
9.5.1.3
LED Default Configuration Based on Device Mode
9.5.1.4
Straps for RGMII/SGMII to Copper
9.5.1.5
Straps for RGMII to 1000Base-X
9.5.1.6
Straps for RGMII to 100Base-FX
9.5.1.7
Straps for Bridge Mode (SGMII-RGMII)
9.5.1.8
Straps for 100M Media Convertor
9.5.1.9
Straps for 1000M Media Convertor
9.5.2
LED Configuration
9.5.3
Reset Operation
9.5.3.1
Hardware Reset
9.5.3.2
IEEE Software Reset
9.5.3.3
Global Software Reset
9.5.3.4
Global Software Restart
9.6
Register Maps
9.6.1
DP83869 Registers
10
Application and Implementation
10.1
Application Information
10.2
Typical Applications
10.2.1
Copper Ethernet Typical Application
10.2.1.1
Design Requirements
10.2.1.2
Detailed Design Procedure
10.2.1.2.1
Clock Input
10.2.1.2.1.1
Crystal Recommendations
10.2.1.2.1.2
External Clock Source Recommendation
10.2.1.2.2
Magnetics Requirements
10.2.1.2.2.1
Magnetics Connection
10.2.1.3
Application Curves
10.2.2
Fiber Ethernet Typical Ethernet
10.2.2.1
Design Requirements
10.2.2.2
Detailed Design Procedure
10.2.2.2.1
Transceiver Connections
10.2.2.3
Application Curves
11
Power Supply Recommendations
11.1
Two-Supply Configuration
11.2
Three-Supply Configuration
12
Layout
12.1
Layout Guidelines
12.1.1
Signal Traces
12.1.1.1
MAC Interface Layout Guidelines
12.1.1.1.1
SGMII Layout Guidelines
12.1.1.1.2
RGMII Layout Guidelines
12.1.1.2
MDI Layout Guidelines
12.1.2
Return Path
12.1.3
Transformer Layout
12.1.4
Metal Pour
12.1.5
PCB Layer Stacking
12.2
Layout Example
13
Device and Documentation Support
13.1
Documentation Support
13.1.1
Related Documentation
13.2
Receiving Notification of Documentation Updates
13.3
Support Resources
13.4
Trademarks
13.5
Electrostatic Discharge Caution
13.6
Glossary
14
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RGZ|48
MPQF123F
Thermal pad, mechanical data (Package|Pins)
Orderable Information
snls614b_oa
1
Features
Multiple operating modes
Media support: copper and fiber
Media conversion between copper and fiber
Bridge between RGMII and SGMII
Maximum ambient temperature available of 125°C
Exceeds 8-kV IEC61000-4-2 ESD
Low power consumption
< 150 mW for 1000Base-X
< 500 mW for 1000Base-T
Low RGMII latency
Total latency ≤ 384ns for 1000Base-T
Total latency ≤ 361ns for 100Base-TX
Time Sensitive Network (TSN) compliant
Recovered clock output for SyncE
Selectable synchronized clock output: 25 MHz and 125 MHz
SFF-8431 V4.1, 1000BASE-X and 100BASE-FX Compatible
IEEE1588 support via SFD
Wake on LAN support
Configurable IO voltages: 1.8 V, 2.5 V, and 3.3 V
SGMII, RGMII, MII MAC interface
Jumbo frame support for 1000M and 100M speed
Cable diagnostics
TDR
BIST
Programmable RGMII termination impedance
Integrated MDI termination resistor
Fast link drop modes
Conforms to IEEE 802.3 1000Base-T, 100Base-TX, 10Base-Te,1000Base-X, 100Base-FX