JAJSMN5 July 2021 ADC09DJ800-Q1 , ADC09QJ800-Q1 , ADC09SJ800-Q1
PRODUCTION DATA
The device can be programmed for a number JESD204C output formats. #GUID-4926C6B4-F6FC-4A8B-92BE-857233B4F132/SBAS9601154 summarizes the basic operating mode configuration parameters and whether they are user configured or derived.
PARAMETER | DESCRIPTION | USER CONFIGURED OR DERIVED | VALUE |
---|---|---|---|
JMODE | JESD204C operating mode, automatically derives the rest of the JESD204C parameters | User configured | Set by JMODE |
R | Number of bits transmitted per lane per ADC core sampling clock cycle. The JESD204C line rate is the sampling clock frequency (fS) times R. This parameter sets the SerDes PLL multiplication factor. | Derived | See #GUID-4926C6B4-F6FC-4A8B-92BE-857233B4F132/X1438, #GUID-4926C6B4-F6FC-4A8B-92BE-857233B4F132/X7750 and #GUID-4926C6B4-F6FC-4A8B-92BE-857233B4F132/X3005 |
K | Number of frames per multiframe (8B/10B mode) | User configured | Set by KM1, see the allowed values in #GUID-4926C6B4-F6FC-4A8B-92BE-857233B4F132/X1438, #GUID-4926C6B4-F6FC-4A8B-92BE-857233B4F132/X7750 and #GUID-4926C6B4-F6FC-4A8B-92BE-857233B4F132/X3005. This parameter is ignored in 64B/66B modes. |
E | Number of multiblocks per extended multiblock (64B/66B mode) | Derived | Always set to '1' in ADC09xJ800-Q1. This parameter is ignored in 8B/10B modes. |
There are a number of parameters required to define the JESD204C transport layer format, all of which are sent across the link during the initial lane alignment sequence in 8B/10B mode. 64B/66B mode does not use the ILAS, however the transport layer uses the same parameters. In the device, most parameters are automatically derived based on the selected JMODE; however, a few are configured by the user. #GUID-4926C6B4-F6FC-4A8B-92BE-857233B4F132/SBAS9608213 describes these parameters.
PARAMETER | DESCRIPTION | USER CONFIGURED OR DERIVED | VALUE |
---|---|---|---|
ADJCNT | LMFC adjustment amount (not applicable) | Derived | Always 0 |
ADJDIR | LMFC adjustment direction (not applicable) | Derived | Always 0 |
BID | Bank ID | Derived | Always 0 |
CF | Number of control words per frame | Derived | Always 0 |
CS | Control bits per sample | Derived | Always set to 0 in ILAS, see #GUID-4926C6B4-F6FC-4A8B-92BE-857233B4F132/X1438, #GUID-4926C6B4-F6FC-4A8B-92BE-857233B4F132/X7750 and #GUID-4926C6B4-F6FC-4A8B-92BE-857233B4F132/X3005 for actual usage |
DID | Device identifier, used to identify the link | User configured | Set by DID, see #GUID-4926C6B4-F6FC-4A8B-92BE-857233B4F132/SBAS9601197 |
F | Number of octets (bytes) per frame (per lane) | Derived | See #GUID-4926C6B4-F6FC-4A8B-92BE-857233B4F132/X1438, #GUID-4926C6B4-F6FC-4A8B-92BE-857233B4F132/X7750 and #GUID-4926C6B4-F6FC-4A8B-92BE-857233B4F132/X3005 |
HD | High-density format (samples split between lanes) | Derived | Always 0 |
JESDV | JESD204 standard revision | Derived | Always 1 |
K | Number of frames per multiframe | User configured | Set by the KM1 register |
L | Number of serial output lanes per link | Derived | See #GUID-4926C6B4-F6FC-4A8B-92BE-857233B4F132/X1438, #GUID-4926C6B4-F6FC-4A8B-92BE-857233B4F132/X7750 and #GUID-4926C6B4-F6FC-4A8B-92BE-857233B4F132/X3005 |
LID | Lane identifier for each lane | Derived | See #GUID-4926C6B4-F6FC-4A8B-92BE-857233B4F132/SBAS9601197 |
M | Number of converters used to determine lane bit packing; may not match number of ADC channels in the device | Derived | See #GUID-4926C6B4-F6FC-4A8B-92BE-857233B4F132/X1438, #GUID-4926C6B4-F6FC-4A8B-92BE-857233B4F132/X7750 and #GUID-4926C6B4-F6FC-4A8B-92BE-857233B4F132/X3005 |
N | Sample resolution (before adding control and tail bits) | Derived | See #GUID-4926C6B4-F6FC-4A8B-92BE-857233B4F132/X1438, #GUID-4926C6B4-F6FC-4A8B-92BE-857233B4F132/X7750 and #GUID-4926C6B4-F6FC-4A8B-92BE-857233B4F132/X3005 |
N' | Bits per sample after adding control and tail bits | Derived | See #GUID-4926C6B4-F6FC-4A8B-92BE-857233B4F132/X1438, #GUID-4926C6B4-F6FC-4A8B-92BE-857233B4F132/X7750 and #GUID-4926C6B4-F6FC-4A8B-92BE-857233B4F132/X3005 |
S | Number of samples per converter (M) per frame | Derived | See #GUID-4926C6B4-F6FC-4A8B-92BE-857233B4F132/X1438, #GUID-4926C6B4-F6FC-4A8B-92BE-857233B4F132/X7750 and #GUID-4926C6B4-F6FC-4A8B-92BE-857233B4F132/X3005 |
SCR | Scrambler enabled | User configured | Set by SCR |
SUBCLASSV | Device subclass version | Derived | Always 1 |
RES1 | Reserved field 1 | Derived | Always 0 |
RES2 | Reserved field 2 | Derived | Always 0 |
CHKSUM | Checksum for ILAS checking (sum of all above parameters modulo 256) | Derived | Computed based on parameters in this table |
Configuring the device is made easy by using a single configuration parameter called JMODE. Using #GUID-4926C6B4-F6FC-4A8B-92BE-857233B4F132/X1438 for the quad channel device, #GUID-4926C6B4-F6FC-4A8B-92BE-857233B4F132/X7750 for the dual channel device or #GUID-4926C6B4-F6FC-4A8B-92BE-857233B4F132/X3005 for the single channel device, the correct JMODE value can be found for the desired operating mode. The modes listed are the only available operating modes. This tables also gives a range and allowable step size for the K parameter (set by KM1), which sets the multiframe length in number of frames.
OPERATING MODE | USER-SPECIFIED PARAMETER | DERIVED PARAMETERS | INPUT CLOCK RANGE (MHz) | ||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
JMODE | K [Min:Step:Max] | Encoding | N | CS | N’ | CF | L | M | F | S | HD | E | R (Fbit / Fclk) | ||
9-Bit, 8B/10B, 8 Lanes | 0 | 4:4:256 | 8B/10B | 12(3) | 0 | 12 | 0 | 8 | 8(1) | 8 | 5 | 0 | — | 8 | 500-800 |
9-Bit, 8B/10B, 6 Lanes | 1 | 16:16:256 | 8B/10B | 12(3) | 0 | 12 | 0 | 6 | 4 | 2 | 2 | 1 | — | 10 | 500-800 |
8-Bit, 8B/10B, 4 Lanes | 2 | 32:32:256 | 8B/10B | 8 | 0 | 8 | 0 | 4 | 4 | 1 | 1 | 0 | — | 10 | 500-800 |
9-Bit, 8B/10B, 4 Lanes | 3 | 32:32:256 | 8B/10B | 10(3) | 0 | 10 | 0 | 4 | 4 | 5 | 4 | 0 | — | 12.5 | 500-800 |
9-Bit, 64B/66B, 3 Lanes | 4 | 128(2) | 64B/66B | 12(3) | 0 | 12 | 0 | 3 | 4 | 2 | 1 | 1 | 3 | 16.5 | 500-800 |
8-Bit, 64B/66B, 2 Lanes | 5 | 128(2) | 64B/66B | 8 | 0 | 8 | 0 | 2 | 4 | 2 | 1 | 0 | 1 | 16.5 | 500-800 |
9-Bit, 64B/66B, 6 Lanes | 6 | 128(2) | 64B/66B | 12(3) | 0 | 12 | 0 | 6 | 4 | 2 | 2 | 1 | 3 | 8.25 | 500-800 |
8-Bit, 64B/66B, 4 Lanes | 7 | 256(2) | 64B/66B | 8 | 0 | 8 | 0 | 4 | 4 | 1 | 1 | 0 | 1 | 8.25 | 500-800 |
9-Bit, 64B/66B, 4 Lanes | 8 | 256(2) | 64B/66B | 12(3) | 0 | 12 | 0 | 4 | 4 | 3 | 2 | 0 | 3 | 12.375 | 500-800 |
8-Bit, 8B/10B, 8 Lanes | 9 | 32:32:256 | 8B/10B | 8 | 0 | 8 | 0 | 8 | 4 | 1 | 2 | 0 | — | 5 | 500-800 |
9-Bit, 8B/10B, 8 Lanes | 10 | 32:32:256 | 8B/10B | 10(3) | 0 | 10 | 0 | 8 | 8(1) | 5 | 4 | 0 | — | 6.25 | 500-800 |
9-Bit, 64B/66B, 8 Lanes | 14 | 256(2) | 64B/66B | 12(3) | 0 | 12 | 0 | 8 | 8(1) | 3 | 2 | 0 | 3 | 6.1875 | 500-800 |
OPERATING MODE | USER-SPECIFIED PARAMETER | DERIVED PARAMETERS | INPUT CLOCK RANGE (MHz) | ||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
JMODE | K [Min:Step:Max] | Encoding | N | CS | N’ | CF | L | M | F | S | HD | E | R (Fbit / Fclk) | ||
9-Bit, 8B/10B, 4 Lanes | 0 | 4:4:256 | 8B/10B | 12(3) | 0 | 12 | 0 | 4 | 4(1) | 8 | 5 | 0 | — | 8 | 500-800 |
9-Bit, 8B/10B, 3 Lanes | 1 | 16:16:256 | 8B/10B | 12(3) | 0 | 12 | 0 | 3 | 2 | 2 | 2 | 1 | — | 10 | 500-800 |
8-Bit, 8B/10B, 2 Lanes | 2 | 32:32:256 | 8B/10B | 8 | 0 | 8 | 0 | 2 | 2 | 1 | 1 | 0 | — | 10 | 500-800 |
9-Bit, 8B/10B, 2 Lanes | 3 | 32:32:256 | 8B/10B | 10(3) | 0 | 10 | 0 | 2 | 2 | 5 | 4 | 0 | — | 12.5 | 500-800 |
9-Bit, 64B/66B, 2 Lanes | 4 | 128(2) | 64B/66B | 12(3) | 0 | 12 | 0 | 2 | 2 | 2 | 1 | 1 | 3 | 16.5 | 500-800 |
8-Bit, 64B/66B, 1 Lane | 5 | 128(2) | 64B/66B | 8 | 0 | 8 | 0 | 1 | 2 | 2 | 1 | 0 | 1 | 16.5 | 500-800 |
9-Bit, 64B/66B, 3 Lanes | 6 | 128(2) | 64B/66B | 12(3) | 0 | 12 | 0 | 3 | 2 | 2 | 2 | 1 | 3 | 8.25 | 500-800 |
8-Bit, 64B/66B, 2 Lanes | 7 | 256(2) | 64B/66B | 8 | 0 | 8 | 0 | 2 | 2 | 1 | 1 | 0 | 1 | 8.25 | 500-800 |
9-Bit, 64B/66B, 2 Lanes | 8 | 256(2) | 64B/66B | 12(3) | 0 | 12 | 0 | 2 | 2 | 3 | 2 | 0 | 3 | 12.375 | 500-800 |
8-Bit, 8B/10B, 4 Lanes | 9 | 32:32:256 | 8B/10B | 8 | 0 | 8 | 0 | 3 | 2 | 1 | 2 | 0 | — | 5 | 500-800 |
9-Bit, 8B/10B, 4 Lanes | 10 | 32:32:256 | 8B/10B | 10(3) | 0 | 10 | 0 | 4 | 4(1) | 5 | 4 | 0 | — | 6.25 | 500-800 |
9-Bit, 8B/10B, 8 Lanes | 11 | 4:4:256 | 8B/10B | 12(3) | 0 | 12 | 0 | 8 | 8(1) | 8 | 5 | 0 | — | 4 | 500-800 |
8-Bit, 8B/10B, 8 Lanes | 12 | 32:32:256 | 8B/10B | 8 | 0 | 8 | 0 | 8 | 2 | 1 | 4 | 0 | — | 2.5 | 500-800 |
9-Bit, 8B/10B, 8 Lanes | 13 | 32:32:256 | 8B/10B | 10(3) | 0 | 10 | 0 | 8 | 8(1) | 5 | 4 | 0 | — | 3.125 | 500-800 |
9-Bit, 64B/66B, 4 Lanes | 14 | 256(2) | 64B/66B | 12(3) | 0 | 12 | 0 | 4 | 4(1) | 3 | 2 | 0 | 3 | 6.1875 | 500-800 |
9-Bit, 64B/66B, 8 Lanes | 15 | 256(2) | 64B/66B | 12(3) | 0 | 12 | 0 | 8 | 8(1) | 3 | 2 | 2 | 2 | 3.09375 | 500-800 |
OPERATING MODE | USER-SPECIFIED PARAMETER | DERIVED PARAMETERS | INPUT CLOCK RANGE (MHz) | ||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
JMODE | K [Min:Step:Max] | Encoding | N | CS | N’ | CF | L | M | F | S | HD | E | R (Fbit / Fclk) | ||
9-Bit, 8B/10B, 2 Lanes | 0 | 4:4:256 | 8B/10B | 12(3) | 0 | 12 | 0 | 2 | 2(1) | 8 | 5 | 0 | — | 8 | 500-800 |
9-Bit, 8B/10B, 2 Lanes | 1 | 16:16:256 | 8B/10B | 12(3) | 0 | 12 | 0 | 2 | 1 | 2 | 2 | 1 | — | 10 | 500-800 |
8-Bit, 8B/10B, 2 Lanes | 2 | 32:32:256 | 8B/10B | 8 | 0 | 8 | 0 | 1 | 4 | 1 | 1 | 0 | — | 10 | 500-800 |
9-Bit, 8B/10B, 1 Lane | 3 | 32:32:256 | 8B/10B | 10(3) | 0 | 10 | 0 | 1 | 4 | 5 | 4 | 0 | — | 12.5 | 500-800 |
9-Bit, 64B/66B, 1 Lane | 4 | 128(2) | 64B/66B | 12(3) | 0 | 12 | 0 | 1 | 4 | 2 | 1 | 1 | 3 | 16.5 | 500-800 |
8-Bit, 64B/66B, 1 Lanes | 5 | 128(2) | 64B/66B | 8 | 0 | 8 | 0 | 1 | 4 | 2 | 1 | 0 | 1 | 16.5 | 500-800 |
9-Bit, 64B/66B, 2 Lanes | 6 | 128(2) | 64B/66B | 12(3) | 0 | 12 | 0 | 2 | 4 | 2 | 2 | 1 | 3 | 8.25 | 500-800 |
8-Bit, 64B/66B, 1 Lane | 7 | 256(2) | 64B/66B | 8 | 0 | 8 | 0 | 1 | 4 | 1 | 1 | 0 | 1 | 8.25 | 500-800 |
9-Bit, 64B/66B, 1 Lane | 8 | 256(2) | 64B/66B | 12(3) | 0 | 12 | 0 | 1 | 4 | 3 | 2 | 0 | 3 | 12.375 | 500-800 |
8-Bit, 8B/10B, 2 Lanes | 9 | 32:32:256 | 8B/10B | 8 | 0 | 8 | 0 | 2 | 4 | 1 | 2 | 0 | — | 5 | 500-800 |
9-Bit, 8B/10B, 2 Lanes | 10 | 32:32:256 | 8B/10B | 10(3) | 0 | 10 | 0 | 2 | 2(1) | 5 | 4 | 0 | — | 6.25 | 500-800 |
9-Bit, 8B/10B, 4 Lanes | 11 | 4:4:256 | 8B/10B | 12(3) | 0 | 12 | 0 | 4 | 4(1) | 8 | 5 | 0 | — | 4 | 500-800 |
8-Bit, 8B/10B, 4 Lanes | 12 | 32:32:256 | 8B/10B | 8 | 0 | 8 | 0 | 4 | 1 | 1 | 4 | 0 | — | 2.5 | 500-800 |
9-Bit, 8B/10B, 4 Lanes | 13 | 32:32:256 | 8B/10B | 12(3) | 0 | 10 | 0 | 4 | 4(1) | 5 | 4 | 0 | — | 3.125 | 500-800 |
9-Bit, 64B/66B, 2 Lanes | 14 | 256(2) | 64B/66B | 12(3) | 0 | 12 | 0 | 2 | 2(1) | 3 | 2 | 0 | 3 | 6.1875 | 500-800 |
9-Bit, 64B/66B, 4 Lanes | 15 | 256(2) | 64B/66B | 12(3) | 0 | 12 | 0 | 4 | 4(1) | 3 | 2 | 2 | 2 | 3.09375 | 500-800 |
The quad and dual channel devices have a total of 8 high-speed output drivers and the single channel device a total of 4 high-speed output drivers. The lanes and their derived configuration parameters are described in #GUID-4926C6B4-F6FC-4A8B-92BE-857233B4F132/SBAS9601197. For a specified JMODE, the lowest indexed lanes are used and the higher indexed lanes are automatically powered down. Always route the lowest indexed lanes to the logic device.