SNAS466G February   2009  – December 2016 ADC10D1000QML-SP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Converter Electrical Characteristics: Static Converter Characteristics
    6. 6.6  Converter Electrical Characteristics: Dynamic Converter Characteristics
    7. 6.7  Converter Electrical Characteristics: Analog Input/Output and Reference Characteristics
    8. 6.8  Converter Electrical Characteristics: Channel-to-Channel Characteristics
    9. 6.9  Converter Electrical Characteristics: LVDS CLK Input Characteristics
    10. 6.10 Electrical Characteristics: AutoSync Feature
    11. 6.11 Converter Electrical Characteristics: Digital Control and Output Pin Characteristics
    12. 6.12 Converter Electrical Characteristics: Power Supply Characteristics (1:2 Demux Mode)
    13. 6.13 Converter Electrical Characteristics: AC Electrical Characteristics
    14. 6.14 Timing Requirements: Serial Port Interface
    15. 6.15 Timing Requirements: Calibration
    16. 6.16 Quality Conformance Inspection
    17. 6.17 Timing Diagrams
    18. 6.18 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Features
        1. 7.3.1.1 Input Control and Adjust
          1. 7.3.1.1.1 AC- and DC-Coupled Modes
          2. 7.3.1.1.2 Input Full-Scale Range Adjust
          3. 7.3.1.1.3 Input Offset Adjust
          4. 7.3.1.1.4 DES/Non-DES Mode
          5. 7.3.1.1.5 Sampling Clock Phase Adjust
          6. 7.3.1.1.6 LC Filter-On Input Clock
          7. 7.3.1.1.7 VCMO Adjust
        2. 7.3.1.2 Output Control and Adjust
          1. 7.3.1.2.1 DDR Clock Phase
          2. 7.3.1.2.2 LVDS Output Differential Voltage
          3. 7.3.1.2.3 LVDS Output Common-Mode Voltage
          4. 7.3.1.2.4 Output Formatting
          5. 7.3.1.2.5 Demux/Non-Demux Mode
          6. 7.3.1.2.6 Test Pattern Mode
        3. 7.3.1.3 Calibration Feature
          1. 7.3.1.3.1 Calibration Pins
          2. 7.3.1.3.2 How to Initiate a Calibration Event
          3. 7.3.1.3.3 On-Command Calibration
          4. 7.3.1.3.4 Calibration Adjust
          5. 7.3.1.3.5 Calibration and Power Down
          6. 7.3.1.3.6 Read/Write Calibration Settings
        4. 7.3.1.4 Power Down
      2. 7.3.2 Power-On Reset
    4. 7.4 Device Functional Modes
      1. 7.4.1 Control Modes
        1. 7.4.1.1 Non-Extended Control Mode
          1. 7.4.1.1.1 Non-Demultiplexed Mode Pin (NDM)
          2. 7.4.1.1.2 Dual Data-Rate Phase Pin (DDRPh)
          3. 7.4.1.1.3 Calibration Pin (CAL)
          4. 7.4.1.1.4 Power-Down I-Channel Pin (PDI)
          5. 7.4.1.1.5 Power-Down Q-Channel Pin (PDQ)
          6. 7.4.1.1.6 Test Pattern Mode Pin (TPM)
          7. 7.4.1.1.7 Full-Scale Input Range Pin (FSR)
          8. 7.4.1.1.8 AC-DC-Coupled Mode Pin (VCMO)
          9. 7.4.1.1.9 LVDS Output Common-Mode Pin (VBG)
      2. 7.4.2 Extended Control Mode
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
    6. 7.6 Register Maps
      1. 7.6.1 Register Definitions
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Analog Inputs
        1. 8.1.1.1 Acquiring the Input
        2. 8.1.1.2 Terminating Unused Analog Inputs
        3. 8.1.1.3 Reference Voltage and FSR
        4. 8.1.1.4 Out-of-Range Indication
        5. 8.1.1.5 AC-Coupled Input Signals
        6. 8.1.1.6 DC-Coupled Input Signals
        7. 8.1.1.7 Single-Ended Input Signals
      2. 8.1.2 Clock Inputs
        1. 8.1.2.1 CLK Coupling
        2. 8.1.2.2 CLK Frequency
        3. 8.1.2.3 CLK Level
        4. 8.1.2.4 CLK Duty Cycle
        5. 8.1.2.5 CLK Jitter
        6. 8.1.2.6 CLK Layout
      3. 8.1.3 The LVDS Outputs
        1. 8.1.3.1 Common-Mode and Differential Voltage
        2. 8.1.3.2 Output Data Rate
      4. 8.1.4 Synchronizing Multiple ADC10D1000S in a System
        1. 8.1.4.1 AutoSync Feature
        2. 8.1.4.2 DCLK Reset Feature
  9. 9 Power Supply Recommendations
    1. 9.1 Power Planes
      1. 9.1.1 Bypass Capacitors
        1. 9.1.1.1 Ground Plane
        2. 9.1.1.2 Power Supply Example
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Mounting Recommendation
    2. 10.2 Layout Example
    3. 10.3 Thermal Management
    4. 10.4 Temperature Sensor Diode
    5. 10.5 Radiation Environments
      1. 10.5.1 Total Ionizing Dose
      2. 10.5.2 Single Event Latch-Up and Functional Interrupt
      3. 10.5.3 Single Event Upset
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
        1. 11.1.2.1 Specification Definitions
    2. 11.2 Related Links
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Engineering Samples

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • NAA|376
サーマルパッド・メカニカル・データ
発注情報

9 Power Supply Recommendations

9.1 Power Planes

Source all supply buses for the ADC from a common linear voltage regulator. This ensures that all power buses to the ADC are turned on and off simultaneously. This single source is split into individual sections of the power plane, with individual decoupling and connection to the different power supply buses of the ADC. Due to the low voltage but relatively high supply current requirement, the optimal solution may be to use a switching regulator to provide an intermediate low voltage, which is then regulated down to the final ADC supply voltage by a linear regulator. Refer to the documentation provided for the ADC10D1000RB for additional details on specific regulators that TI recommends for this configuration.

Provide power for the ADC through a broad plane, which is located on one layer adjacent to the ground plane(s). Placing the power and ground planes on adjacent layers provides low impedance decoupling of the ADC supplies, especially at higher frequencies. The output of a linear regulator must feed into the power plane through a low impedance multi-via connection. Split the power plane into individual power peninsulas near the ADC. Each peninsula should feed a particular power bus on the ADC, with decoupling for that power bus connecting the peninsula to the ground plane near each power/ground pin pair. Using this technique can be difficult on many printed circuit CAD tools. To work around this, 0-Ω resistors can be used to connect the power source net to the individual nets for the different ADC power buses. As a final step, the 0-Ω resistors can be removed, and the plane and peninsulas can be connected manually after all other error checking is completed.

9.1.1 Bypass Capacitors

The general recommendation is to have one 100-nF capacitor for each power/ground pin pair. The capacitors must be surface mount multi-layer ceramic chip capacitors similar to Presidio SR0402X7R104KENG5.

9.1.1.1 Ground Plane

Grounding must be done using continuous full ground planes to minimize the impedance for all ground return paths, and provide the shortest possible image/return path for all signal traces.

9.1.1.2 Power Supply Example

The ADC10D1000RB uses continuous ground planes (except where clear areas are needed to provide appropriate impedance management for specific signals), see Figure 49. Power is provided on one plane, with the 1.9-V ADC supply being split into multiple zones or peninsulas for the specific power buses of the ADC. Decoupling capacitors are connected between these power bus peninsulas and the adjacent power planes using vias. The capacitors are located as close to the individual power/ground pin pairs of the ADC as possible. In most cases, this means the capacitors are located on the opposite side of the PCB to the ADC.

ADC10D1000QML-SP 30071802.gif Figure 49. Power and Grounding Example