製品詳細

Sample rate (Max) (MSPS) 1000, 2000 Resolution (Bits) 10 Number of input channels 2, 1 Interface type Parallel LVDS Analog input BW (MHz) 2800 Features Ultra High Speed Rating Space Input range (Vp-p) 0.8 Power consumption (Typ) (mW) 2770 Architecture Folding Interpolating SNR (dB) 56.8 ENOB (Bits) 9 SFDR (dB) 67.6 Operating temperature range (C) -55 to 125, 25 to 25 Input buffer Yes
Sample rate (Max) (MSPS) 1000, 2000 Resolution (Bits) 10 Number of input channels 2, 1 Interface type Parallel LVDS Analog input BW (MHz) 2800 Features Ultra High Speed Rating Space Input range (Vp-p) 0.8 Power consumption (Typ) (mW) 2770 Architecture Folding Interpolating SNR (dB) 56.8 ENOB (Bits) 9 SFDR (dB) 67.6 Operating temperature range (C) -55 to 125, 25 to 25 Input buffer Yes
CCGA (NAA) 376
  • Total Ionizing Dose 100 krad(Si)
  • Single Event Latch-Up 120 Mev-cm2/mg
  • Excellent Accuracy and Dynamic Performance
  • Low Power Consumption
  • R/W SPI Interface for Extended Control Mode
  • Internally Terminated, Buffered, Differential Analog Inputs
  • Ability to Interleave the 2 Channels to Operate 1 Channel at Twice the Conversion Rate
  • Test Patterns at Output for System Debug
  • Programmable 15-Bit Gain and 12-Bit Plus Sign Offset Adjustments
  • Option of 1:2 Demuxed or 1:1 Non-demuxed LVDS Outputs
  • Auto-sync Feature for Multi-chip Systems
  • Single 1.9 ±0.1-V Power Supply
  • 376 Ceramic Pin Grid Array Package (28.2 mm x 28.2 mm x 3.1 mm with 1.27 mm ball-pitch)
  • Total Ionizing Dose 100 krad(Si)
  • Single Event Latch-Up 120 Mev-cm2/mg
  • Excellent Accuracy and Dynamic Performance
  • Low Power Consumption
  • R/W SPI Interface for Extended Control Mode
  • Internally Terminated, Buffered, Differential Analog Inputs
  • Ability to Interleave the 2 Channels to Operate 1 Channel at Twice the Conversion Rate
  • Test Patterns at Output for System Debug
  • Programmable 15-Bit Gain and 12-Bit Plus Sign Offset Adjustments
  • Option of 1:2 Demuxed or 1:1 Non-demuxed LVDS Outputs
  • Auto-sync Feature for Multi-chip Systems
  • Single 1.9 ±0.1-V Power Supply
  • 376 Ceramic Pin Grid Array Package (28.2 mm x 28.2 mm x 3.1 mm with 1.27 mm ball-pitch)

The ADC10D1000 is the latest advance in TI's Ultra-High-Speed ADC family of products. This low-power, high-performance CMOS analog-to-digital converter digitizes signals at 10-bit resolution at sampling rates of up to 1.0 GSPS in dual channel mode or 2.0 GSPS in single channel mode. The ADC10D1000 achieves excellent accuracy and dynamic performance while consuming a typical 2.9 W of power. This space grade, Radiation Tolerant part is rad hard to a single event latch up level of greater than 120MeV and a total dose (TID) of 100 krad(Si). The product is packaged in a hermatic 376 column thermally enhanced CPGA package rated over the temperature range of -55°C to +125°C.

The ADC10D1000 builds upon the features, architecture and functionality of the 8-bit GHz family of ADCs. New features include an auto-sync feature for multi-chip synchronization, independent programmable15-bit gain and 12-bit offset adjustment per channel, LC tank filter on the clock input, and the option of two's complement format for the digital output data. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal track-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 8.9 Effective Number of Bits (ENOB) with a 498 MHz input signal and a 1.0 GHz sample rate while providing a 10−18 Code Error Rate (C.E.R.) Consuming a typical 2.9 W in Non-Demultiplex Mode at 1.0 GSPS from a single 1.9-V supply, this device is ensured to have no missing codes over the full operating temperature range.

Each channel has its own independent DDR Data Clock, DCLKI and DCLKQ, which are in phase when both channels are powered up, so that only one Data Clock could be used to capture all data, which is sent out at the same rate as the input sample clock. If the 1:2 Demultiplexed Mode is selected, a second 10-bit LVDS bus becomes active for each channel, such that the output data rate is sent out two times slower, but two times wider to relax data-capture timing margin. The two channels (I and Q) can also be interleaved (DES Mode) and used as a single 2.0 GSPS ADC to sample on the Q input. The output formatting is offset binary or two's complement and the Low Voltage Differential Signaling (LVDS) digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8 V and 1.2 V.

The ADC10D1000 is the latest advance in TI's Ultra-High-Speed ADC family of products. This low-power, high-performance CMOS analog-to-digital converter digitizes signals at 10-bit resolution at sampling rates of up to 1.0 GSPS in dual channel mode or 2.0 GSPS in single channel mode. The ADC10D1000 achieves excellent accuracy and dynamic performance while consuming a typical 2.9 W of power. This space grade, Radiation Tolerant part is rad hard to a single event latch up level of greater than 120MeV and a total dose (TID) of 100 krad(Si). The product is packaged in a hermatic 376 column thermally enhanced CPGA package rated over the temperature range of -55°C to +125°C.

The ADC10D1000 builds upon the features, architecture and functionality of the 8-bit GHz family of ADCs. New features include an auto-sync feature for multi-chip synchronization, independent programmable15-bit gain and 12-bit offset adjustment per channel, LC tank filter on the clock input, and the option of two's complement format for the digital output data. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal track-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 8.9 Effective Number of Bits (ENOB) with a 498 MHz input signal and a 1.0 GHz sample rate while providing a 10−18 Code Error Rate (C.E.R.) Consuming a typical 2.9 W in Non-Demultiplex Mode at 1.0 GSPS from a single 1.9-V supply, this device is ensured to have no missing codes over the full operating temperature range.

Each channel has its own independent DDR Data Clock, DCLKI and DCLKQ, which are in phase when both channels are powered up, so that only one Data Clock could be used to capture all data, which is sent out at the same rate as the input sample clock. If the 1:2 Demultiplexed Mode is selected, a second 10-bit LVDS bus becomes active for each channel, such that the output data rate is sent out two times slower, but two times wider to relax data-capture timing margin. The two channels (I and Q) can also be interleaved (DES Mode) and used as a single 2.0 GSPS ADC to sample on the Q input. The output formatting is offset binary or two's complement and the Low Voltage Differential Signaling (LVDS) digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8 V and 1.2 V.

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種類 タイトル 最新の英語版をダウンロード 日付
* データシート ADC10D1000QML Low-Power, 10-Bit, Dual 1-GSPS or Single 2-GSPS Analog-to-Digital Converter データシート (Rev. G) PDF | HTML 2016年 12月 7日
* 放射線と信頼性レポート ADC SEU Test Method 2012年 5月 7日
* 放射線と信頼性レポート ADC10D1000CCMLS SEE Report 2012年 5月 7日
* 放射線と信頼性レポート ADC10D1000CCMLS TID Report 2012年 5月 7日
* 放射線と信頼性レポート CMOS Low Dose Rate Paper 2012年 5月 7日
* 放射線と信頼性レポート ADC08D1520WGRQV Low Dose Rate Test Paper 2012年 5月 4日
セレクション・ガイド TI Space Products (Rev. I) 2022年 3月 3日
アプリケーション・ノート 376-pin column grid array temperature cycle report final PDF | HTML 2021年 6月 14日
アプリケーション・ノート Heavy Ion Orbital Environment Single-Event Effects Estimations 2020年 5月 18日
アプリケーション・ノート Single-Event Effects Confidence Interval Calculations 2020年 1月 14日
その他の技術資料 TI Engineering Evaluation Units vs. MIL-PRF-38535 QML Class V Processing 2019年 6月 17日
e-Book(PDF) Radiation Handbook for Electronics (Rev. A) 2019年 5月 21日
アプリケーション・ノート AN-2132 Synchronizing Multiple GSPS ADCs in a System: The AutoSync Feature (Rev. G) 2017年 2月 3日
アプリケーション・ノート Signal Chain Noise Figure Analysis 2014年 10月 29日
アプリケーション・ノート Synchronizing the Giga Sample ADCs interfaced with multiple FPGAs 2014年 8月 6日
アプリケーション・ノート AN-2128 ADC1xD1x00 Pin Compatibility (Rev. C) 2013年 5月 1日
アプリケーション・ノート ADC10D1500 Synchrzng Multiple GSPS ADCs in a System: AutoSync Feature 2012年 12月 18日
その他の技術資料 ADC12Dxx00RF Direct RF-Sampling ADC Family 2012年 5月 16日

設計および開発

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評価ボード

ADC-LD-BB — ADC 低歪バラン・ボード

One ADC-LD-BB board is included in the hardware kit with the GSPS analog-to-digital converter (ADC) reference boards. Since the analog inputs to the ADC1xDxx00RB are differential and most signal sources are single ended, these balun boards are generally used to achieve (...)

ユーザー・ガイド: PDF
TI.com で取り扱いなし
評価ボード

ADC-WB-BB — ADC 広帯域バラン・ボード

One ADC-WB-BB board is included in the hardware kit with the GSPS analog-to-digital converter (ADC) reference boards. Since the analog inputs to the ADC1xDxx00RB are differential and most signal sources are single ended, these balun boards are generally used to achieve (...)

ユーザー・ガイド: PDF
TI.com で取り扱いなし
評価ボード

ADC10D1000CVAL — 10 ビット、2回路 1.0 GSPS/ 1回路 2.0 GSPS 信号取得 評価ボード

The ADC10D1000CVAL Evaluation Board populated with a ceramic sample is designed to allow quick evaluation and design development of TI's ADC10D1000CCMLS ultra high speed 10-bit Analog-to-Digital Converter. This evaluation board is designed to function with Agilent's 16702B Logic Analysis System for (...)

シミュレーション・モデル

ADC10D1000QML IBIS Model

SNAM012.ZIP (42 KB) - IBIS Model
シミュレーション・ツール

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PSpice® for TI は、各種アナログ回路の機能評価に役立つ、設計とシミュレーション向けの環境です。設計とシミュレーションに適したこのフル機能スイートは、Cadence® のアナログ分析エンジンを使用しています。PSpice for TI は無償で使用でき、アナログや電源に関する TI の製品ラインアップを対象とする、業界でも有数の大規模なモデル・ライブラリが付属しているほか、選択された一部のアナログ動作モデルも利用できます。

設計とシミュレーション向けの環境である PSpice for TI (...)
パッケージ ピン数 ダウンロード
CCGA (NAA) 376 オプションの表示

購入と品質

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  • デバイスのマーキング
  • リード端子の仕上げ / ボールの原材料
  • MSL rating / リフローピーク温度
  • MTBF/FIT 推定値
  • 原材料組成
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