JAJSGZ4 February 2019 ADC3244E
PRODUCTION DATA.
The signal-to-noise ratio of the ADC is limited by three different factors, as shown in Equation 1. Quantization noise (typically 86 dB for a 14-bit ADC) and thermal noise limit SNR at low input frequencies while the clock jitter sets SNR for higher input frequencies.
The SNR limitation resulting from sample clock jitter can be calculated with Equation 2.
The total clock jitter (tJitter) has two components: the internal aperture jitter (130 fs for the device) that is set by the noise of the clock input buffer and the external clock. tJitter can be calculated with Equation 3.
External clock jitter can be minimized by using high-quality clock sources and jitter cleaners as well as bandpass filters at the clock input while a faster clock slew rate improves the ADC aperture jitter. The ADC3244E has a typical thermal noise of 73.5 dBFS and internal aperture jitter of 130 fs. Figure 48 shows SNR (from 1 MHz offset leaving the 1/f flicker noise) for different jitter of clock driver.