JAJSK68A October   2020  – May 2022 ADC3641 , ADC3642 , ADC3643

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Consumption
    6. 6.6  Electrical Characteristics - DC Specifications
    7. 6.7  Electrical Characteristics - AC Specifications ADC3641
    8. 6.8  Electrical Characteristics - AC Specifications ADC3642
    9. 6.9  Electrical Characteristics - AC Specifications ADC3643
    10. 6.10 Timing Requirements
    11. 6.11 Typical Characteristics - ADC3641
    12. 6.12 Typical Characteristics - ADC3642
    13. 6.13 Typical Characteristics - ADC3643
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
        1. 8.3.1.1 Analog Input Bandwidth
        2. 8.3.1.2 Analog Front End Design
          1. 8.3.1.2.1 Sampling Glitch Filter Design
          2. 8.3.1.2.2 Single Ended Input
          3. 8.3.1.2.3 Analog Input Termination and DC Bias
            1. 8.3.1.2.3.1 AC-Coupling
            2. 8.3.1.2.3.2 DC-Coupling
        3. 8.3.1.3 Auto-Zero Feature
      2. 8.3.2 Clock Input
        1. 8.3.2.1 Single Ended vs Differential Clock Input
        2. 8.3.2.2 Signal Acquisition Time Adjust
      3. 8.3.3 Voltage Reference
        1. 8.3.3.1 Internal voltage reference
        2. 8.3.3.2 External voltage reference (VREF)
        3. 8.3.3.3 External voltage reference with internal buffer (REFBUF)
      4. 8.3.4 Digital Down Converter
        1. 8.3.4.1 DDC MUX
        2. 8.3.4.2 Digital Filter Operation
          1. 8.3.4.2.1 FS/4 Mixing with Real Output
        3. 8.3.4.3 Numerically Controlled Oscillator (NCO) and Digital Mixer
        4. 8.3.4.4 Decimation Filter
        5. 8.3.4.5 SYNC
        6. 8.3.4.6 Output Formatting with Decimation
          1. 8.3.4.6.1 Parallel CMOS
          2. 8.3.4.6.2 Serialized CMOS
      5. 8.3.5 Digital Interface
        1. 8.3.5.1 Parallel CMOS Output
        2. 8.3.5.2 Serialized CMOS output
          1. 8.3.5.2.1 SDR Output Clocking
        3. 8.3.5.3 Output Data Format
        4. 8.3.5.4 Output Formatter
        5. 8.3.5.5 Output Bit Mapper
        6. 8.3.5.6 Output Interface/Mode Configuration
          1. 8.3.5.6.1 Configuration Example
      6. 8.3.6 Test Pattern
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal operation
      2. 8.4.2 Power Down Options
    5. 8.5 Programming
      1. 8.5.1 Configuration using PINs only
      2. 8.5.2 Configuration using the SPI interface
        1. 8.5.2.1 Register Write
        2. 8.5.2.2 Register Read
    6. 8.6 Register Maps
      1. 8.6.1 Detailed Register Description
  9. 9 Application and Implementation
    1. 9.1 Typical Application
      1. 9.1.1 Design Requirements
      2. 9.1.2 Detailed Design Procedure
        1. 9.1.2.1 Input Signal Path
        2. 9.1.2.2 Sampling Clock
        3. 9.1.2.3 Voltage Reference
      3. 9.1.3 Application Curves
    2. 9.2 Initialization Set Up
      1. 9.2.1 Register Initialization During Operation
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.6 Register Maps

Table 8-14 Register Map Summary
REGISTER
ADDRESS		REGISTER DATA
A[11:0]D7D6D5D4D3D2D1D0
0x000000000RESET
0x07OP IF MAPPER0OP IF ENOP IF SEL
0x0800PDN CLKBUFPDN REFAMP0PDN APDN BPDN GLOBAL
0x0ACMOS OB DIS [7:0]
0x0BCMOS OB DIS [15:8]
0x0CCMOS OB DIS [23:16]
0x0D0000MASK CLKBUFMASK REFAMPMASK BG DIS0
0x0ESYNC PIN ENSPI SYNCSPI SYNC EN0REF CTRLREF SELSE CLK EN
0x1100SE ASE B0DLL PDN0AZ EN
0x130000000E-FUSE LD
0x14CUSTOM PAT [7:0]
0x15CUSTOM PAT [15:8]
0x16TEST PAT BTEST PAT ACUSTOM PAT [17:16]
0x18000DCLKIN EN0000
0x19FCLK SRC00FCLK DIV00FCLK ENTOG FCLK
0x1BMAPPER EN20B ENBIT MAPPER RES000
0x1E00CMOS DCLK DEL0000
0x1FLOW DR ENDCLKIN EN0DCLK OB EN2X DCLK000
0x20FCLK PAT [7:0]
0x21FCLK PAT [15:8]
0x22 0 0 0 0 FCLK PAT [19:16]
0x2400CH AVG ENDDC MUXDIG BYPDDC EN0
0x25DDC MUX ENDECIMATIONREAL OUT00MIX PHASE
0x26MIX GAIN AMIX RES AFS/4 MIX AMIX GAIN BMIX RES BFS/4 MIX B
0x27000OP ORDER AQ-DEL AFS/4 MIX PH A00
0x2ANCO A [7:0]
0x2BNCO A [15:8]
0x2CNCO A [23:16]
0x2DNCO A [31:24]
0x2E000OP ORDER BQ-DEL BFS/4 MIX PH B00
0x31NCO B [7:0]
0x32NCO B [15:8]
0x33NCO B [23:16]
0x34NCO B [31:24]
0x39..0x60 OUTPUT BIT MAPPER CHA
0x61..0x88 OUTPUT BIT MAPPER CHB
0x8F000000FORMAT A0
0x92000000FORMAT B0