JAJSG65B September   2018  – December 2018 ADS1278-SP

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      概略回路図
  4. 改訂履歴
  5. 概要(続き)
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements: SPI Format
    7. 7.7 Timing Requirements: Frame-Sync Format
    8. 7.8 Quality Conformance Inspection
    9. 7.9 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Sampling Aperture Matching
      2. 8.3.2  Frequency Response
        1. 8.3.2.1 High-Speed, Low-Power, And Low-Speed Modes
        2. 8.3.2.2 High-Resolution Mode
      3. 8.3.3  Phase Response
      4. 8.3.4  Settling Time
      5. 8.3.5  Data Format
      6. 8.3.6  Analog Inputs (AINP, AINN)
      7. 8.3.7  Voltage Reference Inputs (VREFP, VREFN)
      8. 8.3.8  Clock Input (CLK)
      9. 8.3.9  Mode Selection (MODE)
      10. 8.3.10 Synchronization (SYNC)
      11. 8.3.11 Power-Down (PWDN)
      12. 8.3.12 Format[2:0]
      13. 8.3.13 Serial Interface Protocols
      14. 8.3.14 SPI Serial Interface
        1. 8.3.14.1 SCLK
        2. 8.3.14.2 DRDY/FSYNC (SPI Format)
        3. 8.3.14.3 DOUT
        4. 8.3.14.4 DIN
      15. 8.3.15 Frame-Sync Serial Interface
        1. 8.3.15.1 SCLK
        2. 8.3.15.2 DRDY/FSYNC (Frame-Sync Format)
        3. 8.3.15.3 DOUT
        4. 8.3.15.4 DIN
      16. 8.3.16 DOUT Modes
        1. 8.3.16.1 TDM Mode
        2. 8.3.16.2 TDM Mode, Fixed-Position Data
        3. 8.3.16.3 TDM Mode, Dynamic Position Data
        4. 8.3.16.4 Discrete Data Output Mode
      17. 8.3.17 Daisy-Chaining
      18. 8.3.18 Modulator Output
      19. 8.3.19 Pin Test Using Test[1:0] Inputs
      20. 8.3.20 VCOM Output
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントの更新通知を受け取る方法
    2. 12.2 コミュニティ・リソース
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Power-Down (PWDN)

The channels of the ADS1278-SP can be independently powered down by use of the PWDN inputs. To enter the power-down mode, hold the respective PWDN pin low for at least two CLK cycles. To exit power-down, return the corresponding PWDN pin high. Note that when all channels are powered down, the ADS1278-SP enters a microwatt (μW) power state where all internal biasing is disabled. In this state, the TEST[1:0] input pins must be driven; all other input pins can float. The ADS1278-SP outputs remain driven.

As shown in Figure 71 and Table 10, a maximum of 130 conversion cycles must elapse for SPI interface, and 129 conversion cycles must elapse for Frame-Sync, before reading data after exiting power-down. Data from channels already running are not affected. The user software can perform the required delay time in any of the following ways:

  1. Count the number of data conversions after taking the PWDN pin high.
  2. Delay 129/fDATA or 130/fDATA after taking the PWDN pins high, then read data.
  3. Detect for non-zero data in the powered-up channel.

After powering up one or more channels, the channels are synchronized to each other. It is not necessary to use the SYNC pin to synchronize them.

When a channel is powered down in TDM data format, the data for that channel are either forced to zero (fixed-position TDM data mode) or replaced by shifting the data from the next channel into the vacated data position (dynamic-position TDM data mode).

In Discrete data format, the data are always forced to zero. When powering-up a channel in dynamic-position TDM data format mode, the channel data remain packed until the data are ready, at which time the data frame is expanded to include the just-powered channel data. See the Data Format section for details.

ADS1278-SP ai_pd_time_bas367.gifFigure 71. Power-Down Timing

Table 10. Power-Down Timing

SYMBOL DESCRIPTION MIN TYP MAX UNITS
tPWDN PWDN pulse width to enter Power-Down mode 2 CLK periods
tNDR Time for new data ready (SPI) 129 130 Conversions (1/fDATA)
tNDR Time for new data ready (Frame-Sync) 128 129 Conversions (1/fDATA)