JAJSHV5B June   2017  – August 2019 ADS1287

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      機能ブロック図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Noise Performance
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Analog Input and Multiplexer
      2. 9.3.2 Programmable Gain Amplifier (PGA)
      3. 9.3.3 Modulator
        1. 9.3.3.1 Modulator Overrange
      4. 9.3.4 Voltage Reference Inputs (REFP, REFN)
      5. 9.3.5 Digital Filter
        1. 9.3.5.1 Sinc Filter Stage
        2. 9.3.5.2 FIR Filter Stage
        3. 9.3.5.3 Group Delay and Step Response
          1. 9.3.5.3.1 Linear Phase Response
          2. 9.3.5.3.2 Minimum Phase Response
        4. 9.3.5.4 HPF Stage
      6. 9.3.6 Reset (RESET Pin and Reset Command)
      7. 9.3.7 Master Clock Input (CLK)
    4. 9.4 Device Functional Modes
      1. 9.4.1  Operational Mode
      2. 9.4.2  Chop Mode
      3. 9.4.3  Offset
      4. 9.4.4  Power-Down Mode
      5. 9.4.5  Standby Mode
      6. 9.4.6  Synchronization
        1. 9.4.6.1 Pulse-Sync Mode
        2. 9.4.6.2 Continuous-Sync Mode
      7. 9.4.7  Reading Data
        1. 9.4.7.1 Read-Data-Continuous Mode (RDATAC)
        2. 9.4.7.2 Stop-Read-Data-Continuous-Mode (SDATAC)
      8. 9.4.8  Conversion Data Format
      9. 9.4.9  Offset and Full-Scale Calibration Registers
        1. 9.4.9.1 OFC[2:0] Registers
        2. 9.4.9.2 FSC[2:0] Registers
      10. 9.4.10 Calibration Command
        1. 9.4.10.1 OFSCAL Command
        2. 9.4.10.2 GANCAL Command
      11. 9.4.11 User Calibration
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
        1. 9.5.1.1 Chip Select (CS)
        2. 9.5.1.2 Serial Clock (SCLK)
        3. 9.5.1.3 Data Input (DIN)
        4. 9.5.1.4 Data Output (DOUT)
        5. 9.5.1.5 Serial Interface Timeout
        6. 9.5.1.6 Data Ready (DRDY)
      2. 9.5.2 Commands
        1. 9.5.2.1  WAKEUP: Wake Up Command
        2. 9.5.2.2  STANDBY: Standby Mode Command
        3. 9.5.2.3  SYNC: Synchronize ADC Conversions
        4. 9.5.2.4  RESET: Reset Command
        5. 9.5.2.5  RDATAC: Read Data Continuous Mode Command
        6. 9.5.2.6  SDATAC: Stop Read Data Continuous Mode Command
        7. 9.5.2.7  RDATA: Read Data Command
        8. 9.5.2.8  RREG: Read Register Data Command
        9. 9.5.2.9  WREG: Write Register Data Command
        10. 9.5.2.10 OFSCAL: Offset Calibration Command
        11. 9.5.2.11 GANCAL: Gain Calibration Command
    6. 9.6 Register Map
      1. 9.6.1 Register Descriptions
        1. 9.6.1.1 ID/CFG: ID, Configuration Register (address = 00h) [reset = x0h]
          1. Table 22. ID/CFG Register Field Descriptions
        2. 9.6.1.2 CONFIG0: Configuration Register 0 (address = 01h) [reset = 52h]
          1. Table 23. CONFIG0 Register Field Descriptions
        3. 9.6.1.3 CONFIG1: Configuration Register 1 (address = 02h) [reset = 08h]
          1. Table 24. CONFIG1 Register Field Descriptions
        4. 9.6.1.4 High-Pass Filter Corner Frequency (HPFx) Registers (address = 03h, 04h) [reset = 32h, 03h]
          1. Table 25. HPF0, HPF1 Registers Field Description
        5. 9.6.1.5 Offset Calibration (OFCx) Registers (address = 05h, 06h, 07h) [reset = 00h, 00h, 00h]
          1. Table 26. OFC0, OFC1, OFC2 Registers Field Description
        6. 9.6.1.6 Full-Scale Calibration (FSCx) Registers (address = 08h, 09h, 0Ah) [reset = 00h, 00h, 40h]
          1. Table 27. FSC0, FSC1, FSC2 Registers Field Description
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Geophone Application
      2. 10.2.2 Digital Interface
    3. 10.3 Initialization Set Up
  11. 11Power Supply Recommendations
    1. 11.1 Analog Power Supplies
    2. 11.2 Digital Power Supply
    3. 11.3 Power-Supply Sequence
  12. 12Layout
    1. 12.1 Layout Guidelines
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントの更新通知を受け取る方法
    2. 13.2 コミュニティ・リソース
    3. 13.3 商標
    4. 13.4 静電気放電に関する注意事項
    5. 13.5 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RHF|24
サーマルパッド・メカニカル・データ
発注情報

9.4.8 Conversion Data Format

As shown in Table 14, the conversion data are 32 bits in binary two's complement format. The LSB of the data is a redundant sign bit: 0 for positive numbers and 1 for negative numbers. However, when the data are clipped to FS, the LSB = 1 and when the data are clipped to –FS, the LSB = 0. If desired, the data readback can be stopped after 24 bits. In sinc-filter mode, the data are numerically scaled by half.

Table 14. Ideal Output Code Versus Input Signal

INPUT SIGNAL VIN 32-BIT IDEAL OUTPUT CODE(1)
FIR FILTER SINC FILTER(2)
> VREF / Gain 7FFFFFFFh —(3)
VREF / Gain 7FFFFFFEh 3FFFFFFFh
VREF / (Gain · 230 ) 00000002h 00000001h
0 00000000h 00000000h
–VREF / (Gain · 230 ) FFFFFFFFh FFFFFFFFh
–VREF / (Gain · (230/ (230 – 1))) 80000001h C0000000h
< –VREF / (Gain · (230/ (230 – 1))) 80000000h —(3)
(1) Excludes effects of noise, linearity, offset, and gain errors.
(2) As a result of the reduction in oversampling ratio (OSR) related to high data rates of the sinc filter mode, the available ADC resolution correspondingly reduces.
(3) When the full-scale range is exceeded in sinc filter mode, the conversion data exceeds half-scale code (3FFFFFFFh and C0000000h).