A data transfer frame starts with a falling edge of the CS signal. In any frame, the clocks provided on the SCLK pin are used to transfer the output data for the completed conversion. The device has two SDOs (SDO-0x and SDO-1x) for each ADC. For ADC_A, the device provides data on SDO-0A and SDO-1A, whereas for ADC_B, the device provides data on SDO-0B and SDO-1B. The most significant bit (D_n-1x) of the output data is launched on the SDO-1x pins and the MSB-1 (D_n-2x) bit is launched on the SDO-0x pins on the falling edge of CS, any subsequent output bits are launched on the rising edges provided on SCLK. When all output bits of the conversion result are shifted out, the device launches 0's on the subsequent SCLK rising edges. The data transfer frame ends with a rising edge of the CS signal. For detailed timing specifications, see Section 6 and Figure 7-6.

The CS pulse high time determines if the data being read back is with a 0 sample latency or a 1 sample latency. See Figure 6-1 and Figure 6-2 for the respective timing diagrams. The maximum-rated sampling rate of 2.048 MSPS is achieved with a latency-1 data capture.

For ADC_A, x = A. For ADC_B, x = B.

Figure 7-6 Data Transfer Frame for Reading Data