JAJSJG5 July   2020 ADS9226

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Converter Modules
        1. 7.3.1.1 Analog Input With Sample-and-Hold
        2. 7.3.1.2 ADC Transfer Function
      2. 7.3.2 External Reference Voltage
      3. 7.3.3 Reference Buffers
    4. 7.4 Device Functional Modes
      1. 7.4.1 ACQ State
      2. 7.4.2 CNV State
      3. 7.4.3 Output Data Word
      4. 7.4.4 Conversion Control and Data Transfer Frame
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 ADC Input Driver
        1. 8.1.1.1 Charge-Kickback Filter
      2. 8.1.2 Input Amplifier Selection
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Signal Path
      2. 10.1.2 Grounding and PCB Stack-Up
      3. 10.1.3 Decoupling of Power Supplies
      4. 10.1.4 Reference Decoupling
      5. 10.1.5 Analog Input Decoupling
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.6 Timing Requirements

at AVDD = 4 V to 5.5 V, DVDD = 2.35 V to 5.5 V and maximum throughput (unless otherwise noted); minimum and maximum values at TA = –40°C to +125°C; typical values at TA = 25°C, AVDD = 5 V and DVDD = 3.3 V
MIN NOM MAX UNIT
CONVERSION CONTROL
tCycle Cycle time 488 ns
fSample Sampling rate 2048 kSPS
tACQ Acquisition time tCYCLE - 160 ns
tWH_CS Pulse duration: CS high 15 ns
tWL_CS Pulse duration: CS low 15 ns
SPI MODES
fCLK Serial clock frequency 32.768 MHz
tCLK Serial clock time period 1/ fCLK
tPH_CLK SCLK high time 0.45 0.55 tCLK
tPL_CLK SCLK low time 0.45 0.55 tCLK
tSU_CSCK Setup time: CS faling to first SCLK capture edge 14 ns
tHT_CKCS Delay time: last SCLK launch edge to CS rising 8 ns