JAJSMT3C january   2022  – may 2023 AFE7906

PRODUCTION DATA  

  1.   1
  2. 1特長
  3. 2アプリケーション
  4. 3概要
  5. 4概要 (続き)
  6. 5Revision History
  7. 6Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  RF ADC Electrical Characteristics
    6. 6.6  PLL/VCO/Clock Electrical Characteristics
    7. 6.7  Digital Electrical Characteristics
    8. 6.8  Power Supply Electrical Characteristics
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Characteristics
      1. 6.11.1 RX Typical Characteristics 30 MHz and 400 MHz
      2. 6.11.2 RX Typical Characteristics at 800MHz
      3. 6.11.3 RX Typical Characteristics 1.75GHz to 1.9GHz
      4. 6.11.4 RX Typical Characteristics 2.6GHz
      5. 6.11.5 RX Typical Characteristics 3.5GHz
      6. 6.11.6 RX Typical Characteristics 4.9GHz
      7. 6.11.7 RX Typical Characteristics 6.8GHz
      8. 6.11.8 PLL and Clock Typical Characteristics
  8. 7Device and Documentation Support
    1. 7.1 ドキュメントの更新通知を受け取る方法
    2. 7.2 サポート・リソース
    3. 7.3 Trademarks
    4. 7.4 静電気放電に関する注意事項
    5. 7.5 用語集
  9. 8Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.9 Timing Requirements

Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; fADC = 2949.12MSPS; nominal power supplies; 1 tone at -1 dBFS; DSA Attenuation =0dB; SerDes rate = 24.33Gbps; unless otherwise noted.
MIN NOM MAX UNIT
Timing: SYSREF+/-
ts(SYSREF) Setup Time, SYSREF+/- Valid to Rising Edge of CLK+/- 50 ps
th(SYSREF) Hold Time, SYSREF+/- Valid after Rising Edge of CLK+/- 50 ps
Timing: Serial ports
ts(SENB) Setup Time, SENB to Rising Edge of SCLK 15 ns
th(SENB) Hold Time, SENB after last Rising Edge of SCLK (1) 5 + tSCLK ns
ts(SDIO) Setup Time, SDIO valid to Rising Edge of SCLK 15 ns
th(SDIO) Hold Time, SDIO valid after Rising Edge of SCLK 5 ns
t(SCLK)_W Minimum SCLK period: registers write 25 ns
t(SCLK)_R Minimum SCLK period: registers read 50 ns
td(data_out) Minimum Data Output delay after Falling Edge of SCLK 0 ns
Maximum Data Output delay after Falling Edge of SCLK 15 ns
tRESET Minimum RESETZ Pulse Width 1 ms
(1) SDEN\\ need to be held one more extra clock cycle with the last SCLK edge